公开(公告)号：US06472930B1

公开(公告)日：2002-10-29

申请号：US09177503

申请日：1998-10-23

申请人： Yasuo Morimoto ,  Hiroyuki Kono ,  Takahiro Miki

发明人： Yasuo Morimoto ,  Hiroyuki Kono ,  Takahiro Miki

IPC分类号： G05F110

CPC分类号： G05F3/24

摘要： A current generator (CG) is composed of a constant-current-source transistor M1, and transistors (M2, M3). On receipt of control signals (VG2, VG3) respectively from a driver circuit (not shown), the transistors (M2, M3) complementarily operate to function as current switches. Then, damping resistance (R3) is provided between the drain electrode of the transistor (M3) and an output terminal ({overscore (IT)}). The output terminal ({overscore (IT)}) is connected to a ground (GND), while an output terminal (IT) is grounded via an external terminal (R2). Such a structure allows a semiconductor integrated circuit device to reduce its output ringing and further to suppress imperfections resulting from the adoption of the structure to reduce the ringing.

摘要翻译： 电流发生器（CG）由恒流源晶体管M1和晶体管（M2，M3）组成。 分别从驱动电路（未示出）接收到控制信号（VG2，VG3）时，晶体管（M2，M3）互补地工作，起到电流开关的作用。 然后，在晶体管（M3）的漏电极和输出端（{overscore（IT）}之间设置阻尼电阻（R3）。 输出端子（{overscore（IT）}）连接到地（GND），而输出端（IT）通过外部端子（R2）接地。 这种结构允许半导体集成电路器件减少其输出振铃并且进一步抑制由采用该结构导致的减少振铃的缺陷。

公开(公告)号：US07292172B2

公开(公告)日：2007-11-06

申请号：US11214723

申请日：2005-08-31

申请人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

发明人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

IPC分类号： H03M1/66

CPC分类号： H03M1/0604 ,  H03M1/742

摘要： A current driven D/A converter sets an OFF control voltage (BIAS3) for turning off NMOS transistors M12P, M12N, M22P, M22N, M32P and M32N at a voltage close to an ON control voltage (BIAS2). This makes it possible to reduce the swing of the control voltage (ON control voltage-OFF control voltage) of the NMOS transistors, and hence to reduce the noise due to charge injections through parasitic capacitances, and noise of a ground voltage or power supply voltage due to flowing of discharge currents from the parasitic capacitances to the ground or power supply at turn off of the transistors, thereby being able to offer a high performance current driven D/A converter.

摘要翻译： 电流驱动D / A转换器设置用于关闭NMOS晶体管M 12 P，M 12 N，M 22 P，M 22 N，M 32 P和M 32 N的截止控制电压（BIAS 3） ON控制电压（BIAS 2）。 这使得可以减小NMOS晶体管的控制电压（ON控制电压 - 关闭控制电压）的摆动，从而减少由于通过寄生电容的电荷注入引起的噪声，以及接地电压或电源电压的噪声 由于在晶体管截止时由寄生电容放电到地或电源的放电电流的流动，从而能够提供高性能的电流驱动D / A转换器。

公开(公告)号：US20080024340A1

公开(公告)日：2008-01-31

申请号：US11902773

申请日：2007-09-25

申请人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

发明人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

IPC分类号： H03M1/66

CPC分类号： H03M1/0604 ,  H03M1/742

摘要： A current driven D/A converter sets an OFF control voltage (BIAS3) for turning off NMOS transistors M12P, M12N, M22P, M22N, M32P and M32N at a voltage close to an ON control voltage (BIAS2). This makes it possible to reduce the swing of the control voltage (ON control voltage−OFF control voltage) of the NMOS transistors, and hence to reduce the noise due to charge injections through parasitic capacitances, and noise of a ground voltage or power supply voltage due to flowing of discharge currents from the parasitic capacitances to the ground or power supply at turn off of the transistors, thereby being able to offer a high performance current driven D/A converter.

摘要翻译： 电流驱动D / A转换器设置用于关闭NMOS晶体管M 12 P，M 12 N，M 22 P，M 22 N，M 32 P和M 32 N的截止控制电压（BIAS 3） ON控制电压（BIAS 2）。 这使得可以减小NMOS晶体管的控制电压（ON控制电压 - 关闭控制电压）的摆动，从而减少由于通过寄生电容的电荷注入引起的噪声，以及接地电压或电源电压的噪声 由于在晶体管截止时由寄生电容放电到地或电源的放电电流的流动，从而能够提供高性能的电流驱动D / A转换器。

公开(公告)号：US06703957B2

公开(公告)日：2004-03-09

申请号：US10143878

申请日：2002-05-14

申请人： Yasuo Morimoto ,  Toshio Kumamoto ,  Takashi Okuda ,  Takahiro Miki

发明人： Yasuo Morimoto ,  Toshio Kumamoto ,  Takashi Okuda ,  Takahiro Miki

IPC分类号： H03M166

CPC分类号： H03M1/0614 ,  H03K5/01 ,  H03K5/133 ,  H03M1/822 ,  H03M3/372 ,  H03M3/506

摘要： When forming PDM pulses by a D/A converter in accordance with digital signals, the D/A converter causes at least one of the rising stage and the falling stage of each of the PDM pulses to change stepwise. In addition, when forming PWM pulses by another D/A converter, the D/A converter causes at least one of the rising stage and the falling stage of each of the PWM pulses to change stepwise.

摘要翻译： 当通过D / A转换器根据数字信号形成PDM脉冲时，D / A转换器使得每个PDM脉冲的上升沿和下降沿中的至少一个逐步改变。 此外，当由另一个D / A转换器形成PWM脉冲时，D / A转换器使每个PWM脉冲的上升沿和下降沿中的至少一个逐步改变。

公开(公告)号：US20060044169A1

公开(公告)日：2006-03-02

申请号：US11214723

申请日：2005-08-31

申请人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

发明人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

IPC分类号： H03M1/66

CPC分类号： H03M1/0604 ,  H03M1/742

摘要： A current driven D/A converter sets an OFF control voltage (BIAS3) for turning off NMOS transistors M12P, M12N, M22P, M22N, M32P and M32N at a voltage close to an ON control voltage (BIAS2). This makes it possible to reduce the swing of the control voltage (ON control voltage—OFF control voltage) of the NMOS transistors, and hence to reduce the noise due to charge injections through parasitic capacitances, and noise of a ground voltage or power supply voltage due to flowing of discharge currents from the parasitic capacitances to the ground or power supply at turn off of the transistors, thereby being able to offer a high performance current driven D/A converter.

摘要翻译： 电流驱动D / A转换器设置用于在接近ON控制电压（BIAS2）的电压下关断NMOS晶体管M12P，M12N，M22P，M22N，M32P和M32N的OFF控制电压（BIAS3）。 这使得可以减小NMOS晶体管的控制电压（ON控制电压 - 关闭控制电压）的摆动，从而减少由于通过寄生电容的电荷注入引起的噪声，以及接地电压或电源电压的噪声 由于在晶体管截止时由寄生电容放电到地或电源的放电电流的流动，从而能够提供高性能的电流驱动D / A转换器。

公开(公告)号：US08957480B2

公开(公告)日：2015-02-17

申请号：US14003225

申请日：2011-03-04

申请人： Kazuaki Deguchi ,  Yasuo Morimoto ,  Masao Ito

发明人： Kazuaki Deguchi ,  Yasuo Morimoto ,  Masao Ito

IPC分类号： H01L29/00 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02

CPC分类号： H01L27/088 ,  H01L21/823425 ,  H01L27/0207 ,  H01L29/7846

摘要： In a semiconductor device, an active region includes: a first impurity region to which a predetermined voltage is applied; second and third impurity regions forming a pair of conductive electrodes of an insulated gate field effect transistor; and at least one impurity region disposed between the first and second impurity regions. A voltage that causes electrical conduction between the second and third impurity regions is applied to a gate electrode disposed between the second and third impurity regions. All gate electrodes disposed between the first and second impurity regions are configured to be electrically connected to the first impurity region constantly. All impurity regions disposed between the first and second impurity regions are electrically isolated from the first and second impurity regions and maintained in a floating state.

摘要翻译： 在半导体器件中，有源区包括：施加预定电压的第一杂质区; 形成绝缘栅场效应晶体管的一对导电电极的第二和第三杂质区; 以及设置在第一和第二杂质区域之间的至少一个杂质区域。 将引起第二和第三杂质区之间导电的电压施加到设置在第二和第三杂质区之间的栅电极。 设置在第一和第二杂质区域之间的所有栅极电极被配置为恒定地电连接到第一杂质区域。 设置在第一和第二杂质区域之间的所有杂质区域与第一和第二杂质区域电隔离并保持在浮置状态。

公开(公告)号：US20130334609A1

公开(公告)日：2013-12-19

申请号：US14003225

申请日：2011-03-04

申请人： Kazuaki Deguchi ,  Yasuo Morimoto ,  Masao Ito

发明人： Kazuaki Deguchi ,  Yasuo Morimoto ,  Masao Ito

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L21/823425 ,  H01L27/0207 ,  H01L29/7846

摘要： In a semiconductor device, an active region includes: a first impurity region to which a predetermined voltage is applied; second and third impurity regions forming a pair of conductive electrodes of an insulated gate field effect transistor; and at least one impurity region disposed between the first and second impurity regions. A voltage that causes electrical conduction between the second and third impurity regions is applied to a gate electrode disposed between the second and third impurity regions. All gate electrodes disposed between the first and second impurity regions are configured to be electrically connected to the first impurity region constantly. All impurity regions disposed between the first and second impurity regions are electrically isolated from the first and second impurity regions and maintained in a floating state.

摘要翻译： 在半导体器件中，有源区包括：施加预定电压的第一杂质区; 形成绝缘栅场效应晶体管的一对导电电极的第二和第三杂质区; 以及设置在第一和第二杂质区域之间的至少一个杂质区域。 将引起第二和第三杂质区之间导电的电压施加到设置在第二和第三杂质区之间的栅电极。 设置在第一和第二杂质区域之间的所有栅极电极被配置为恒定地电连接到第一杂质区域。 设置在第一和第二杂质区域之间的所有杂质区域与第一和第二杂质区域电隔离并保持在浮置状态。

公开(公告)号：US08237282B2

公开(公告)日：2012-08-07

申请号：US13030861

申请日：2011-02-18

申请人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L23/522

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

公开(公告)号：US20090250788A1

公开(公告)日：2009-10-08

申请号：US12485528

申请日：2009-06-16

申请人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction, a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 形成在主表面上并沿预定方向延伸的电容形成区域中的多个第一互连，多个第二互连，每个第二互连相邻于位于电容形成区域边缘的第一互连件，沿预定方向延伸; 并具有固定的潜力; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

公开(公告)号：US07446390B2

公开(公告)日：2008-11-04

申请号：US11845348

申请日：2007-08-27

申请人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。