公开(公告)号：US06703957B2

公开(公告)日：2004-03-09

申请号：US10143878

申请日：2002-05-14

申请人： Yasuo Morimoto ,  Toshio Kumamoto ,  Takashi Okuda ,  Takahiro Miki

发明人： Yasuo Morimoto ,  Toshio Kumamoto ,  Takashi Okuda ,  Takahiro Miki

IPC分类号： H03M166

CPC分类号： H03M1/0614 ,  H03K5/01 ,  H03K5/133 ,  H03M1/822 ,  H03M3/372 ,  H03M3/506

摘要： When forming PDM pulses by a D/A converter in accordance with digital signals, the D/A converter causes at least one of the rising stage and the falling stage of each of the PDM pulses to change stepwise. In addition, when forming PWM pulses by another D/A converter, the D/A converter causes at least one of the rising stage and the falling stage of each of the PWM pulses to change stepwise.

摘要翻译： 当通过D / A转换器根据数字信号形成PDM脉冲时，D / A转换器使得每个PDM脉冲的上升沿和下降沿中的至少一个逐步改变。 此外，当由另一个D / A转换器形成PWM脉冲时，D / A转换器使每个PWM脉冲的上升沿和下降沿中的至少一个逐步改变。

公开(公告)号：US07915708B2

公开(公告)日：2011-03-29

申请号：US12485528

申请日：2009-06-16

申请人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

公开(公告)号：US06538589B2

公开(公告)日：2003-03-25

申请号：US10136416

申请日：2002-05-02

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

IPC分类号： H03M300

CPC分类号： H03M7/3006 ,  H03M7/302

摘要： A digital &Dgr;&Sgr; modulator comprises a first-stage 1-bit &Dgr;&Sgr; modulator provided with an 1-bit (1 is an arbitrary natural number) quantizer, for modulating digital data, a correction logic for multiplying a quantization error caused in the 1-bit quantizer by a correction so that the quantization error caused in the 1-bit quantizer is eliminated at an output of the first-stage 1-bit &Dgr;&Sgr; modulator, and a next-stage m-bit &Dgr;&Sgr; modulator provided with an m-bit (m is an arbitrary natural number larger than 1) quantizer, for modulating and feeding the quantization error which is multiplied by the correction by the correction logic back to the first-stage 1-bit &Dgr;&Sgr; modulator.

摘要翻译： 一个数字DELTASIGMA调制器包括一个第一级1位DELTASIGMA调制器，它配备1位（1为任意自然数）量化器，用于调制数字数据;一个校正逻辑，用于将1位量化器中引起的量化误差相乘 通过校正，使得在第一级1位DELTASIGMA调制器的输出处消除在1位量化器中引起的量化误差，并且提供具有m位的下一级m位DELTASIGMA调制器（m是 大于1）量化器的任意自然数，用于将与校正逻辑的校正相乘的量化误差调制和馈送回到第一级1位DELTASIGMA调制器。

公开(公告)号：US07557427B2

公开(公告)日：2009-07-07

申请号：US11845339

申请日：2007-08-27

申请人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L51/05

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

公开(公告)号：US20070296059A1

公开(公告)日：2007-12-27

申请号：US11845339

申请日：2007-08-27

申请人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

公开(公告)号：US06809582B2

公开(公告)日：2004-10-26

申请号：US10615932

申请日：2003-07-10

申请人： Yasuo Morimoto ,  Toshio Kumamoto ,  Takashi Okuda

发明人： Yasuo Morimoto ,  Toshio Kumamoto ,  Takashi Okuda

IPC分类号： G06G712

CPC分类号： H01L27/0255 ,  H01L27/0203 ,  H03F1/523 ,  H03F2200/444 ,  H03F2203/45568 ,  H03K5/2481

摘要： Two groups of diodes are connected to internal lines transmitting complementary signals, respectively, and positions of the centers of gravity of the groups of diodes are made coincident with each other. A circuit capable of preventing the deviation of the characteristics of differential transistor pair caused by an antenna effect and highly immune against a substrate noise can be achieved.

摘要翻译： 两组二极管分别连接到传输互补信号的内部线路，并且二极管组的重心位置彼此一致。 可以实现能够防止由天线效应引起的差分晶体管对的特性偏离并且高度免于衬底噪声的电路。

公开(公告)号：US06734816B2

公开(公告)日：2004-05-11

申请号：US10408238

申请日：2003-04-08

申请人： Yasuo Morimoto ,  Toshio Kumamoto ,  Takashi Okuda

发明人： Yasuo Morimoto ,  Toshio Kumamoto ,  Takashi Okuda

IPC分类号： H03M166

CPC分类号： H03M3/372 ,  H03M3/502

摘要： A D/A converter including a plurality of potential generating sections. They each receive a 1-bit signal from one of an input terminal and delay circuit, and a clock signal or inverted clock signal from an input section or inverter for inverting the clock signal. When the clock signal or inverted clock signal is at a first signal level, they generate a first reference potential or second reference potential in response to the signal level of the 1-bit signal. When the clock signal or inverted clock signal is at the second level, they generate an intermediate potential between the first and second reference potentials. The potentials generated by the plurality of potential generating sections are combined by a combining section. The D/A converter can improve resistance to jitter, and to simplify the configuration of a post-stage filter circuit.

摘要翻译： 一种D / A转换器，包括多个电位产生部分。 它们各自从输入端和延迟电路之一接收1位信号，以及来自用于反相时钟信号的输入部分或反相器的时钟信号或反相时钟信号。 当时钟信号或反相时钟信号处于第一信号电平时，它们响应于1位信号的信号电平而产生第一参考电位或第二参考电位。 当时钟信号或反相时钟信号处于第二电平时，它们在第一和第二参考电位之间产生中间电位。 由多个电位产生部分产生的电位由组合部分组合。 D / A转换器可以提高抗抖动性，并简化后级滤波电路的配置。

公开(公告)号：US20110140277A1

公开(公告)日：2011-06-16

申请号：US13030861

申请日：2011-02-18

申请人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L23/522

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

公开(公告)号：US07009539B2

公开(公告)日：2006-03-07

申请号：US10715456

申请日：2003-11-19

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

IPC分类号： H03M3/00

CPC分类号： H03M3/46 ,  H03M3/418 ,  H03M3/454 ,  H03M3/50 ,  H03M7/3022 ,  H03M7/3028 ,  H03M7/304

摘要： A ΔΣ modulator modulates only an error component separated by a component separating portion. Therefore, even if the number of order of the ΔΣ modulator increases, an amplitude of an output of an integrator in the final stage does not excessively increase, and the stability of the modulator can be achieved. Since the signal component separated by the component separating portion does not pass through the ΔΣ modulator, an intensity of an input signal can be maintained as it is, and the modulator can have high precision.

摘要翻译： DeltaSigma调制器仅调制由分量分离部分分离的误差分量。 因此，即使DeltaSigma调制器的次数增加，最终级的积分器的输出的幅度也不会过度增加，并且可以实现调制器的稳定性。 由于由分量分离部分分离的信号分量不通过ΔΣ调制器，所以可以保持输入信号的强度，并且调制器可以具有高精度。

公开(公告)号：US08237282B2

公开(公告)日：2012-08-07

申请号：US13030861

申请日：2011-02-18

申请人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L23/522

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。