公开(公告)号：US06472715B1

公开(公告)日：2002-10-29

申请号：US09675109

申请日：2000-09-28

申请人： Yauh-Ching Liu ,  Helmut Puchner ,  Ruggero Castagnetti ,  Weiran Kong ,  Lee Phan ,  Franklin Duan ,  Steven Michael Peterson

发明人： Yauh-Ching Liu ,  Helmut Puchner ,  Ruggero Castagnetti ,  Weiran Kong ,  Lee Phan ,  Franklin Duan ,  Steven Michael Peterson

IPC分类号： H01L2976

CPC分类号： H01L21/823892 ,  H01L27/11

摘要： An integrated circuit structures such as an SRAM construction wherein the soft error rate is reduced comprises an integrated circuit structure formed in a semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to one or more deep N wells connected to the high voltage supply and the deep N wells extend from the surface of the substrate down into the substrate to a depth at least equal to that depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell. For a 0.25 &mgr;m SRAM design having one or more N wells of a conventional depth not exceeding about 0.5 &mgr;m, the depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell is from 1 to 3 &mgr;m. The deep N well of the 0.25 &mgr;m SRAM design, therefore, extends down from the substrate surface a distance of at least about 1 &mgr;m, and preferably at least about 2 &mgr;m. In a preferred embodiment, the implantation of the substrate to form the deep N well of the improved SRAM of the invention is carried out in a manner which will cause straggle, i.e., cause the doped volume comprising the deep N well to broaden at its base. Such a broadened base deep N well will have enhanced opportunity to collect electrons generated by the alpha particle collision with the substrate. This deep N well with a broadened base can be formed either by increasing the implant energy or by tilting the substrate with respect to the axis of the implant beam while implanting the substrate to form the deep N well.

摘要翻译： 诸如SRAM结构的集成电路结构，其中软错误率被降低包括形成在半导体衬底中的集成电路结构，其中至少一个N沟道晶体管被构建在邻近一个或多个深N阱的P阱中， 高压电源和深N阱从衬底的表面向下延伸到衬底中的至少等于α粒子产生的电子 - 空穴对可以有效地引起SRAM单元中的软错误的深度的深度。 对于具有一个或多个常规深度不超过约0.5μm的N个阱的0.25μmSRAM设计，α粒子产生的电子 - 空穴对可以有效地引起SRAM单元中的软误差的深度为1至3μm 。 因此，0.25μmSRAM设计的深N阱从衬底表面向下延伸至少约1um，优选至少约2μm的距离。 在优选实施例中，衬底的注入以形成本发明的改进的SRAM的深N阱以将导致分段的方式进行，即，使得包括深N阱的掺杂体积在其基极处变宽 。 这样扩大的基底深N阱将增加收集由α粒子与基底碰撞产生的电子的机会。 可以通过增加植入能量或通过相对于植入物束的轴线倾斜衬底同时植入衬底以形成深N阱来形成具有加宽基底的该深N阱。

公开(公告)号：US6144076A

公开(公告)日：2000-11-07

申请号：US207395

申请日：1998-12-08

申请人： Helmut Puchner ,  Shih-Fen Huang ,  Ruggero Castagnetti

发明人： Helmut Puchner ,  Shih-Fen Huang ,  Ruggero Castagnetti

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/76

CPC分类号： H01L21/823892 ,  H01L21/76237 ,  H01L27/0921

摘要： A multiple well formation is provided in a CMOS region of a semiconductor substrate to provide enhanced latchup protection for one or more CMOS transistors formed in the wells. The structure comprises an N well extending from the substrate surface down into the substrate, a buried P well formed in the substrate beneath the N well, a second P well extending from the substrate surface down into the substrate, and an isolation region formed in the substrate between the N well and the second P well. The buried P well may extend beneath both the N well and the second P well in the substrate. In a preferred embodiment of the invention, the N well and the second P well are each implanted in the substrate at an energy level sufficient to provide a dopant concentration peak in the substrate below the depth of the isolation region to provide punch through protection and to provide a channel stop beneath the isolation region by proving a P-N junction between the N well and P well beneath the isolation region. The dopant concentration level peak of the dopants forming the buried P well in the substrate will be located below the dopant concentration level peak of the N well a minimum distance sufficient to inhibit reduction of the effective depth of the N well, and a maximum distance not exceeding the maximum distance which will still provide enhanced latchup protection to one or more transistors formed in the CMOS region.

摘要翻译： 在半导体衬底的CMOS区域中提供多阱形成，以为形成在阱中的一个或多个CMOS晶体管提供增强的闭锁保护。 该结构包括从衬底表面向下延伸到衬底中的N阱，在N阱下方的衬底中形成的掩埋P阱，从衬底表面向下延伸到衬底中的第二P阱以及形成在衬底中的隔离区 N阱和第二P阱之间的衬底。 掩埋的P阱可以在衬底中的N阱和第二P阱的下方延伸。 在本发明的一个优选实施方案中，N阱和第二P阱各自以足以在衬底中的掺杂剂浓度峰值（在低于隔离区域的深度）提供掺杂剂浓度峰值的能级注入到衬底中，以提供穿通保护，并且 通过在隔离区之下的N阱和P阱之间提供PN结，在隔离区之下提供通道停止。 在衬底中形成掩埋P阱的掺杂剂的掺杂剂浓度水平峰值将位于N阱的掺杂剂浓度水平峰值以下，其最小距离足以抑制N阱的有效深度的减小，并且最大距离不 超过仍将为在CMOS区域中形成的一个或多个晶体管提供增强的闭锁保护的最大距离。

公开(公告)号：US06455363B1

公开(公告)日：2002-09-24

申请号：US09609527

申请日：2000-07-03

申请人： Helmut Puchner ,  Gary K. Giust ,  Weiran Kong

发明人： Helmut Puchner ,  Gary K. Giust ,  Weiran Kong

IPC分类号： H01L218238

CPC分类号： H01L21/76237 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0921

摘要： A method for fabricating an SRAM device having a standard well tub, where an additional well tub is deposited within the standard well tub. In this manner, the dopant concentration is increased in the well area of the SRAM device, which increases both the isolation punchthrough tolerance and the SER immunity of the device. The additional well tub is deposited to a depth that is shallower than the standard well tub. The additional well tub is deposited using an ion implantation process using the same mask set as that used for the threshold voltage adjustment deposition. Thus, no additional mask layer is required to deposit the additional well tub, and the all of the expenses normally associated with an additional mask layer are avoided.

摘要翻译： 一种用于制造具有标准井筒的SRAM装置的方法，其中在标准井筒内沉积附加的井筒。 以这种方式，SRAM器件的阱区域中的掺杂剂浓度增加，这增加了器件的隔离穿透容限和SER抗扰性。 另外的浴缸被沉积到比标准的井筒浅的深度。 使用与用于阈值电压调整沉积的掩模组相同的掩模组，使用离子注入工艺沉积附加的井筒。 因此，不需要额外的掩模层来沉积附加的井筒，并且避免了与附加掩模层通常相关联的所有费用。

公开(公告)号：US20140006730A1

公开(公告)日：2014-01-02

申请号：US13537877

申请日：2012-06-29

申请人： Suhail Zain ,  Helmut Puchner ,  Walt Anderson ,  Karthik Navalpakam

发明人： Suhail Zain ,  Helmut Puchner ,  Walt Anderson ,  Karthik Navalpakam

IPC分类号： G06F12/00

CPC分类号： G06F13/16 ,  G06F12/00 ,  G06F13/1668 ,  G06F13/1673 ,  G06F13/1694

摘要： A device can include a controller interface having at least one controller data output configured to output read data, and at least one controller data input configured to receive write data; and a memory device interface having a write data output configured to transmit the write data on rising and falling edges of a periodic signal, and a read data input configured to receive the read data at a same transmission rate as the write data.

摘要翻译： 设备可以包括控制器接口，其具有被配置为输出读取数据的至少一个控制器数据输出，以及被配置为接收写入数据的至少一个控制器数据输入; 以及存储器件接口，其具有被配置为在周期信号的上升沿和下降沿发送写入数据的写入数据输出，以及被配置为以与写入数据相同的传输速率接收读取的数据的读取数据输入。

公开(公告)号：US20050215024A1

公开(公告)日：2005-09-29

申请号：US11069501

申请日：2005-03-01

申请人： Jeong-Yeop Nahm ,  Helmut Puchner ,  Oliver Pohland ,  Yangzhong Xu

发明人： Jeong-Yeop Nahm ,  Helmut Puchner ,  Oliver Pohland ,  Yangzhong Xu

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/1045 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： Methods for fabricating diffusion regions having steep concentration profiles within MOS devices while minimizing junction capacitance degradation are provided. In particular, methods are provided which include patterning a gate structure upon a semiconductor substrate and subsequently etching a recess in exposed portions of the substrate. In some cases, the method includes forming a first dopant region within the exposed portions prior to etching the recess. The method may additionally or alternatively include implanting a second set of dopants into portions of the semiconductor substrate bordering the recess. In either case, the method includes growing an epitaxial layer within the recess and implanting a third set of dopants into the semiconductor topography to form a second dopant region extending to a depth at least within the epitaxial layer. A resulting semiconductor topography includes a source/drain region comprising an upper portion consisting essentially of first dopants of a first conductivity type.

摘要翻译： 提供了在MOS器件内制造具有陡峭浓度分布的扩散区，同时最小化结电容劣化的方法。 特别地，提供了包括在半导体衬底上图案化栅极结构并随后蚀刻衬底的暴露部分中的凹部的方法。 在一些情况下，该方法包括在蚀刻凹槽之前在暴露部分内形成第一掺杂区域。 该方法可以附加地或替代地包括将第二组掺杂剂注入到与凹部接合的半导体衬底的部分中。 在任一情况下，该方法包括在凹槽内生长外延层并将第三组掺杂剂注入到半导体形貌中以形成延伸至至少在外延层内的深度的第二掺杂区。 得到的半导体形貌包括源/漏区，其包括基本上由第一导电类型的第一掺杂剂组成的上部。

公开(公告)号：US06831348B2

公开(公告)日：2004-12-14

申请号：US10383031

申请日：2003-03-06

申请人： Helmut Puchner ,  Sheldon Aronowitz

发明人： Helmut Puchner ,  Sheldon Aronowitz

IPC分类号： H01L2900

CPC分类号： H01L21/7621

摘要： A method of forming a narrow isolation structure in a semiconducting substrate. The isolation structure is a trench that has a bottom and sidewalls, and that is to be filled with an isolating material. The isolating material has desired electrical properties and desired chemical properties, and is substantially reactively grown from the semiconducting substrate. A precursor material layer is formed on the bottom of the trench and on the sidewalls of the trench. The precursor material layer has electrical properties and chemical properties that are substantially similar to the desired electrical properties and the desired chemical properties of the isolating material. A substantial portion of the precursor material layer is removed from the bottom of the trench to expose the semiconducting substrate at the bottom of the trench, while leaving a substantial portion of the precursor material layer on the sidewalls of the trench. The isolating material is reactively grown in the trench, where the isolating material preferentially grows from the exposed semiconducting substrate at the bottom of the trench at a first rate. The precursor material layer at least partially inhibits formation of the isolating material from the semiconducting substrate at the sidewalls of the trench. The isolating material forms from the sidewalls of the trench at a second rate, where the first rate is substantially higher than the second rate. Thus, by forming a precursor layer that inhibits formation of the isolation material at the sidewalls of the trench, the isolation material preferentially grows from the bottom of the trench rather than expanding sideways from the sidewalls of the trench, which tends to widen the isolation structure. Because the precursor layer has properties that are substantially similar to those that are desired in the isolation material, the precursor layer remains at the sidewalls of the trench near the edge of the isolation structure. Therefore, the isolation structure functions as desired, but is narrower than it otherwise would be, if the precursor layer had not been formed.

公开(公告)号：US06342429B1

公开(公告)日：2002-01-29

申请号：US09469579

申请日：1999-12-22

申请人： Helmut Puchner ,  Shih-Fen Huang

发明人： Helmut Puchner ,  Shih-Fen Huang

IPC分类号： H01L2176

CPC分类号： H01L21/8238 ,  H01L21/76237

摘要： Provided is a technique for forming an indium field implant at the bottom of an STI trench to strengthen the p-well under field oxide, but to not weaken the n-well under the field oxide. The diffusivity of indium is an order of magnitude smaller than that of boron and the activation level of indium is high enough for well dopings. Thus, the implanted indium is able to keep the concentration of p-dopant at the p-n well junction under the field isolation and the oxide/silicon interface high, even with boron depletion, so that punchthrough is avoided.

摘要翻译： 提供了一种用于在STI沟槽底部形成铟场注入的技术，以加强场氧化物下的p阱，但不会削弱场氧化物下的n阱。 铟的扩散系数比硼的扩散系数小一个数量级，铟的激活电位足够高以使阱掺杂。 因此，即使在硼耗尽的情况下，注入的铟能够在场隔离下保持p-n阱结的p型掺杂浓度，并且氧化物/硅界面也能保持高浓度，从而避免穿透。

公开(公告)号：US08841727B1

公开(公告)日：2014-09-23

申请号：US13620161

申请日：2012-09-14

申请人： Andrew Walker ,  Helmut Puchner ,  Sai Dhanraj ,  Kevin Jang

发明人： Andrew Walker ,  Helmut Puchner ,  Sai Dhanraj ,  Kevin Jang

IPC分类号： H01L23/62

CPC分类号： H01L29/7436 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/0886 ,  H01L29/1016 ,  H01L29/41758 ,  H01L29/42308 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

摘要： A circuit with electrostatic discharge protection is described. In one case, the circuit includes trigger device configured to protect a component connected to a node of the circuit during an electrostatic discharge event, the trigger device includes an isolation structure interposed between a gate oxide layer and an extended drain region. A portion of the extended drain region proximate the isolation structure is substantially metal-free.

摘要翻译： 描述了具有静电放电保护的电路。 在一种情况下，电路包括被配置为在静电放电事件期间保护连接到电路节点的部件的触发装置，触发装置包括插入在栅氧化层和延伸漏极区之间的隔离结构。 靠近隔离结构的延伸漏极区域的一部分基本上是无金属的。

公开(公告)号：US08278684B1

公开(公告)日：2012-10-02

申请号：US11954514

申请日：2007-12-12

申请人： Andrew J. Walker ,  Helmut Puchner

发明人： Andrew J. Walker ,  Helmut Puchner

IPC分类号： H01L29/66

CPC分类号： H01L29/7436 ,  H01L27/0262 ,  H01L29/0603

摘要： A voltage protection device and method is provided to prevent accidental triggering of an silicon-controlled rectifier (SCR) unless the electrostatic discharge (ESD) is at a predefined threshold above the normal power supply operating voltage or below the ground supply operating voltage. The holding voltage upon the SCR is maintained above the threshold voltage to prevent accidental triggering. The present SCR avoids use of an additional field effect transistor (FET), and avoids relying upon the breakdown of the drain terminal of the FET, but instead programs the amount of holding voltage needed above the power supply voltage using mask-programmability, fuses, or other means for maintaining the holding voltage to a desired range above the power supply voltage. The programmed holding voltage is implemented using a barrier region between the PNP and the NPN of the PNPN junctions of the SCR. In addition to or as an alternative to the barrier region, hole sink junctions can be implemented close to the anode to reduce the substrate resistance in the vicinity of the anode and, therefore, extract holes from their normal target destination.

摘要翻译： 提供了一种电压保护装置和方法，以防止硅可控整流器（SCR）的意外触发，除非静电放电（ESD）处于高于正常电源工作电压或低于接地电源工作电压的预定阈值。 SCR上的保持电压保持在阈值电压以上，以防止意外触发。 当前的SCR避免使用附加的场效应晶体管（FET），并且避免依赖于FET的漏极端子的击穿，而是使用掩模可编程性，保险丝来编程所需的高于电源电压的保持电压量， 或用于将保持电压维持在高于电源电压的期望范围的其它装置。 编程的保持电压使用PNP与SCR的PNPN结的NPN之间的屏障区域来实现。 除了作为屏障区域的替代方案之外，可以在阳极附近实现空穴接合点，以降低阳极附近的衬底电阻，并因此从其正常目标目的地提取孔。

公开(公告)号：US08129788B1

公开(公告)日：2012-03-06

申请号：US11656072

申请日：2007-01-22

申请人： Andrew Walker ,  Helmut Puchner

发明人： Andrew Walker ,  Helmut Puchner

IPC分类号： H01L23/62

CPC分类号： H01L27/0262

摘要： A protection circuit and method are provided for protecting semiconductor devices from electrostatic discharge (ESD). Generally, the ESD protection circuit includes a silicon controlled rectifier (SCR) formed in a substrate and configured to transfer charge from a protected node to a negative power supply, VSS, during an ESD event, and a trigger device to activate transfer of charge by the SCR when a voltage on the protected node reaches a predetermined trigger voltage. The trigger device includes a gated-diode and MOS capacitor formed in a well formed in the substrate, the trigger device configured to inject electrons into the well during charging of the MOS capacitor, forward biasing a node of the SCR, hence allowing fast triggering of the SCR device. The trigger voltage can be set independent of a holding voltage by adjusting the length of the well and area of the capacitor. Other embodiments are also disclosed.

摘要翻译： 提供保护电路和方法来保护半导体器件免受静电放电（ESD）的影响。 通常，ESD保护电路包括形成在衬底中并被配置为在ESD事件期间将电荷从受保护节点传递到负电源VSS的触发装置，以及用于激活电荷转移的触发装置 当受保护节点上的电压达到预定触发电压时的SCR。 触发装置包括形成在衬底中的阱中形成的栅极二极管和MOS电容器，触发装置被配置为在MOS电容器充电期间向阱中注入电子，向SCR偏置节点，从而允许快速触发 SCR设备。 触发电压可以通过调整阱的长度和电容器的面积而与保持电压无关。 还公开了其他实施例。