公开(公告)号：US07355246B2

公开(公告)日：2008-04-08

申请号：US11268430

申请日：2005-11-07

申请人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： H01L29/76

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108

摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

摘要翻译： 一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷 第二种载体。 根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。 此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结 是不偏不倚的 一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

公开(公告)号：US06992339B2

公开(公告)日：2006-01-31

申请号：US10750572

申请日：2003-12-31

申请人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： H01L27/10

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L29/7841

摘要： Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

公开(公告)号：US06906973B1

公开(公告)日：2005-06-14

申请号：US10746148

申请日：2003-12-24

申请人： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad M. Khellah ,  Fabrice Paillet ,  Stephen H. Tang ,  Ali Keshavarzi ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad M. Khellah ,  Fabrice Paillet ,  Stephen H. Tang ,  Ali Keshavarzi ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： G11C7/00 ,  G11C7/12

CPC分类号： G11C7/12

摘要： Some embodiments provide pre-charge of a bit-line coupled to a memory cell to a reference voltage using a pre-charge device, discharge of the bit-line based on a value stored by the memory cell, injection during the discharge, of a first current into the bit-line using the pre-charge device, and injection, during the discharge, of a second current into a reference bit-line using a second pre-charge device. Also during the discharge, a difference is sensed between a voltage on the bit-line and a voltage on the reference bit-line.

摘要翻译： 一些实施例使用预充电器件将耦合到存储器单元的位线预充电至参考电压，基于存储器单元存储的值，放电期间的注入，放电期间的位线放电， 使用预充电器件进入位线的第一电流，以及在放电期间使用第二预充电器件将第二电流注入参考位线。 此外，在放电期间，在位线上的电压和参考位线上的电压之间感测到差异。

公开(公告)号：US07072205B2

公开(公告)日：2006-07-04

申请号：US10716755

申请日：2003-11-19

申请人： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： G11C11/24 ,  G11C11/34

CPC分类号： G11C11/4094 ,  G11C11/404 ,  G11C11/4076 ,  G11C11/4085

摘要： A row of floating-body single transistor memory cells is written to in two phases.

摘要翻译： 一行浮体单晶体管存储单元分两个阶段写入。

公开(公告)号：US07001811B2

公开(公告)日：2006-02-21

申请号：US10750566

申请日：2003-12-31

申请人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： H01L21/336

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108

摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

摘要翻译： 一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷 第二种载体。 根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。 此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结 是不偏不倚的 一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

公开(公告)号：US07391640B2

公开(公告)日：2008-06-24

申请号：US11008666

申请日：2004-12-10

申请人： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： G11C11/24 ,  G11C11/34

CPC分类号： G11C11/405 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.

摘要翻译： 动态随机存取存储器包括具有浮体晶体管和位线之间的电路的单元。 控制电路的激活以在写入操作期间和在单元未被选择的时间期间在浮体和位线电压之间提供隔离。 增加的隔离可以提高性能，例如，通过减少门到体耦合的需要和位线之间的电压摆幅的大小。

公开(公告)号：US07123500B2

公开(公告)日：2006-10-17

申请号：US10749734

申请日：2003-12-30

申请人： Yibin Ye ,  Dinesh Somasekhar ,  Muhammad M. Khellah ,  Fabrice Paillet ,  Stephen H. Tang ,  Ali Keshavarzi ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Yibin Ye ,  Dinesh Somasekhar ,  Muhammad M. Khellah ,  Fabrice Paillet ,  Stephen H. Tang ,  Ali Keshavarzi ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： G11C11/24

CPC分类号： G11C11/405

摘要： A two-transistor DRAM cell includes an NMOS device and a PMOS device coupled to the NMOS device.

摘要翻译： 双晶体管DRAM单元包括耦合到NMOS器件的NMOS器件和PMOS器件。

公开(公告)号：US07120072B2

公开(公告)日：2006-10-10

申请号：US10881001

申请日：2004-06-30

申请人： Yibin Ye ,  Dinesh Somasekhar ,  Muhammad M Khellah ,  Fabrice Paillet ,  Stephen H Tang ,  Ali Keshavarzi ,  Shih-Lien L Lu ,  Vivek K De

发明人： Yibin Ye ,  Dinesh Somasekhar ,  Muhammad M Khellah ,  Fabrice Paillet ,  Stephen H Tang ,  Ali Keshavarzi ,  Shih-Lien L Lu ,  Vivek K De

IPC分类号： G11C7/00

CPC分类号： G11C11/405

摘要： A two transistor memory cell includes a write transistor and a read transistor. When reading the memory cell, the read transistor is turned on, and a voltage develops on a read bit line.

摘要翻译： 双晶体管存储单元包括写晶体管和读晶体管。 读取存储单元时，读取晶体管导通，读取位线上产生电压。

公开(公告)号：US07098507B2

公开(公告)日：2006-08-29

申请号：US10879480

申请日：2004-06-30

申请人： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Brian Doyle ,  Suman Datta ,  Vivek K. De

发明人： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Brian Doyle ,  Suman Datta ,  Vivek K. De

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/39

CPC分类号： H01L29/785 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7841

摘要： A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

公开(公告)号：US07061806B2

公开(公告)日：2006-06-13

申请号：US10954931

申请日：2004-09-30

申请人： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C11/4076 ,  G11C2216/14

摘要： A system to write to a plurality of memory cells coupled to a word line, each of the plurality of memory cells comprising a transistor having a source, a drain, a body and a gate coupled to the word line. Some embodiments provide biasing of one or more of the plurality of memory cells in saturation to inject charge carriers into the body of the one or more of the plurality of memory cells, and biasing of each of the plurality of memory cells in accumulation to tunnel charge carriers from the body of each of the plurality of memory cells to the gate of each of the plurality of memory cells.

摘要翻译： 一种写入耦合到字线的多个存储单元的系统，所述多个存储器单元中的每一个包括具有耦合到所述字线的源极，漏极，主体和栅极的晶体管。 一些实施例提供饱和中的多个存储单元中的一个或多个的偏置以将电荷载流子注入多个存储单元中的一个或多个存储器单元的主体中，并且将多个存储单元中的每一个的累积偏压到隧道电荷 载体从多个存储单元的每一个的主体到多个存储单元中的每一个的门。