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21 条记录 (耗时 0.021 秒)

    Buried Layer of An Integrated Circuit
    1.
    发明申请
    Buried Layer of An Integrated Circuit 有权
    集成电路的埋层

    公开(公告)号：US20120326276A1

    公开(公告)日：2012-12-27

    申请号：US13596970

    申请日：2012-08-28

    申请人： Yin-Fu Huang ,  Ming Rong Chang ,  Shih-Chin Lien

    发明人： Yin-Fu Huang ,  Ming Rong Chang ,  Shih-Chin Lien

    IPC分类号： H01L29/06

    CPC分类号： H01L29/7322 ,  H01L21/2652 ,  H01L21/324 ,  H01L21/761 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/167 ,  H01L29/66272 ,  H01L29/78

    摘要： Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed.

    摘要翻译： 该技术的各个方面都针对集成电路制造方法和集成电路。 在一种方法中，通过在半导体材料上通过牺牲氧化物并通过半导体材料的中间区域注入第一电荷型掩埋层的第一电荷型掺杂剂，并通过半导体材料的中间区域转移集成电路的半导体材料中的第一电荷型掩埋层 植入的第一电荷型掺杂剂。 当注入的掺杂剂通过牺牲氧化物时，避免对半导体晶格的损伤。 如果牺牲氧化物不存在，则注入的掺杂剂将已经通过并损坏了半导体晶格。 之后，生长并除去预退火氧化物。

    Buried layer of an integrated circuit
    2.
    发明授权
    Buried layer of an integrated circuit 有权
    埋层的集成电路

    公开(公告)号：US08258042B2

    公开(公告)日：2012-09-04

    申请号：US12549869

    申请日：2009-08-28

    申请人： Yin-Fu Huang ,  Ming Rong Chang ,  Shih-Chin Lien

    发明人： Yin-Fu Huang ,  Ming Rong Chang ,  Shih-Chin Lien

    IPC分类号： H01L21/76

    CPC分类号： H01L29/7322 ,  H01L21/2652 ,  H01L21/324 ,  H01L21/761 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/167 ,  H01L29/66272 ,  H01L29/78

    摘要： Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed.

    摘要翻译： 该技术的各个方面都针对集成电路制造方法和集成电路。 在一种方法中，通过在半导体材料上通过牺牲氧化物并通过半导体材料的中间区域注入第一电荷型掩埋层的第一电荷型掺杂剂，并通过半导体材料的中间区域转移集成电路的半导体材料中的第一电荷型掩埋层 植入的第一电荷型掺杂剂。 当注入的掺杂剂通过牺牲氧化物时，避免对半导体晶格的损伤。 如果牺牲氧化物不存在，则注入的掺杂剂将已经通过并损坏半导体晶格。 之后，生长并除去预退火氧化物。

    Buried layer of an integrated circuit
    3.
    发明授权
    Buried layer of an integrated circuit 有权
    埋层的集成电路

    公开(公告)号：US08507993B2

    公开(公告)日：2013-08-13

    申请号：US13596970

    申请日：2012-08-28

    申请人： Yin-Fu Huang ,  Ming Rong Chang ,  Shih-Chin Lien

    发明人： Yin-Fu Huang ,  Ming Rong Chang ,  Shih-Chin Lien

    IPC分类号： H01L27/092

    CPC分类号： H01L29/7322 ,  H01L21/2652 ,  H01L21/324 ,  H01L21/761 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/167 ,  H01L29/66272 ,  H01L29/78

    摘要： Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed.

    摘要翻译： 该技术的各个方面都针对集成电路制造方法和集成电路。 在一种方法中，集成电路的半导体材料中的第一电荷型掩埋层，其通过半导体材料上的牺牲氧化物并通过半导体材料的中间区域注入第一电荷型掩埋层的第一电荷型掺杂剂，并通过半导体材料的中间区域 植入的第一电荷型掺杂剂。 当注入的掺杂剂通过牺牲氧化物时，避免对半导体晶格的损伤。 如果牺牲氧化物不存在，则注入的掺杂剂将已经通过并损坏半导体晶格。 之后，生长并除去预退火氧化物。

    Buried Layer of An Integrated Circuit
    4.
    发明申请
    Buried Layer of An Integrated Circuit 有权
    集成电路的埋层

    公开(公告)号：US20110049677A1

    公开(公告)日：2011-03-03

    申请号：US12549869

    申请日：2009-08-28

    申请人： Yin-Fu Huang ,  Ming Rong Chang ,  Shih-Chin Lien

    发明人： Yin-Fu Huang ,  Ming Rong Chang ,  Shih-Chin Lien

    IPC分类号： H01L29/06 ,  H01L21/761

    CPC分类号： H01L29/7322 ,  H01L21/2652 ,  H01L21/324 ,  H01L21/761 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/167 ,  H01L29/66272 ,  H01L29/78

    摘要： Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed.

    摘要翻译： 该技术的各个方面都针对集成电路制造方法和集成电路。 在一种方法中，通过在半导体材料上通过牺牲氧化物并通过半导体材料的中间区域注入第一电荷型掩埋层的第一电荷型掺杂剂，并通过半导体材料的中间区域转移集成电路的半导体材料中的第一电荷型掩埋层 植入的第一电荷型掺杂剂。 当注入的掺杂剂通过牺牲氧化物时，避免对半导体晶格的损伤。 如果牺牲氧化物不存在，则注入的掺杂剂将已经通过并损坏半导体晶格。 之后，生长并除去预退火氧化物。

    Semiconductor structure and method for forming the same
    8.
    发明授权
    Semiconductor structure and method for forming the same 有权
    半导体结构及其形成方法

    公开(公告)号：US08643072B1

    公开(公告)日：2014-02-04

    申请号：US13547549

    申请日：2012-07-12

    申请人： Miao-Chun Chung ,  An-Li Cheng ,  Yin-Fu Huang ,  Shih-Chin Lien ,  Shyi-Yuan Wu

    发明人： Miao-Chun Chung ,  An-Li Cheng ,  Yin-Fu Huang ,  Shih-Chin Lien ,  Shyi-Yuan Wu

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7833 ,  H01L29/0619

    摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bulk, a gate, a source, a drain and a bulk contact region. The gate is on the bulk. The source and the drain are in the bulk on opposing sides of the gate respectively. The bulk contact region is only in a region of the bulk adjacent to the source. The bulk contact region is electrically connected to the bulk.

    摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括体，栅极，源极，漏极和体接触区域。 门是大量的。 源极和漏极分别在栅极的相对侧上。 体接触区域仅在与源极相邻的部分的区域中。 体接触区域电连接到本体。

    LDMOS HAVING SINGLE-STRIP SOURCE CONTACT AND METHOD FOR MANUFACTURING SAME
    9.
    发明申请
    LDMOS HAVING SINGLE-STRIP SOURCE CONTACT AND METHOD FOR MANUFACTURING SAME 审中-公开
    具有单条线源的LDMOS接触器及其制造方法

    公开(公告)号：US20120037989A1

    公开(公告)日：2012-02-16

    申请号：US12857288

    申请日：2010-08-16

    申请人： Hsueh-I Huang ,  Shuo-Lun Tu ,  Ming-Tung Lee ,  Yin-Fu Huang ,  Shih-Chin Lien ,  Shyi-Yuan WU

    发明人： Hsueh-I Huang ,  Shuo-Lun Tu ,  Ming-Tung Lee ,  Yin-Fu Huang ,  Shih-Chin Lien ,  Shyi-Yuan WU

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/66689

    摘要： LDMOS devices having a single-strip contact pad in the source region, and related methods of manufacturing are disclosed. The LDMOS may comprise a first well lightly doped with a first dopant and formed into a portion of a substrate, the first well having a drain region at its surface heavily doped with the first dopant, and a second well lightly doped with a second dopant formed in another portion of the substrate, the second well having a source region at its surface comprising first portions heavily doped with the first dopant directly adjacent second portions heavily doped with the second dopant. Also, the LDMOS device may comprise a field oxide at the upper surface of the substrate between the source and drain regions, and contacting the first well but separated from the second well, and a gate formed partially over the field oxide and partially over the source region. The LDMOS may also comprise contact pads in contact with the gate, and source and drain regions, wherein the contact pad in contact with the source regions comprises a single-strip of conductive material extending across the source region.

    摘要翻译： 公开了在源区域中具有单条接触焊盘的LDMOS器件以及相关的制造方法。 LDMOS可以包括轻掺杂有第一掺杂剂并形成衬底的一部分的第一阱，第一阱在其表面上重掺杂有第一掺杂剂的漏极区，以及轻掺杂有第二掺杂剂的第二阱 在衬底的另一部分中，第二阱在其表面处具有源极区，其包括重掺杂有第一掺杂物的第一部分，其与第二掺杂剂重掺杂的第二部分直接相邻。 此外，LDMOS器件可以在源极和漏极区域之间的衬底的上表面处包括场氧化物，并且与第一阱接触但与第二阱分离，并且部分地形成在场氧化物上并部分地在源极上形成的栅极 地区。 LDMOS还可以包括与栅极接触的接触焊盘以及源极和漏极区域，其中与源极区域接触的接触焊盘包括跨越源极区域延伸的单条导电材料。

    High voltage semiconductor device
    10.
    发明授权
    High voltage semiconductor device 有权
    高压半导体器件

    公开(公告)号：US08476705B2

    公开(公告)日：2013-07-02

    申请号：US12962702

    申请日：2010-12-08

    申请人： Hsuehi Huang ,  Yin-Fu Huang ,  Shih-Chin Lien

    发明人： Hsuehi Huang ,  Yin-Fu Huang ,  Shih-Chin Lien

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66689

    摘要： A semiconductor device for a high voltage application includes a doped source base region, an N+ source region, a P+ source region and a gate structure. The doped source base region has P-type. The N+ source region extends downwards into the doped source base region. The P+ source region is close to the N+ source region, extends downwards into the doped source base region, and is doped heavier than the doped source base region. The gate structure is coupled to the N+ source region and is near to the P+ source region.

    摘要翻译： 用于高电压应用的半导体器件包括掺杂源极基极区域，N +源极区域，P +源极区域和栅极结构。 掺杂源极区具有P型。 N +源极区域向下延伸到掺杂源极基极区域中。 P +源极区域靠近N +源极区域，向下延伸到掺杂源极区域中，并且掺杂得比掺杂源极区域重。 栅极结构耦合到N +源极区并且靠近P +源极区。