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    LDMOS HAVING SINGLE-STRIP SOURCE CONTACT AND METHOD FOR MANUFACTURING SAME
    1.
    发明申请
    LDMOS HAVING SINGLE-STRIP SOURCE CONTACT AND METHOD FOR MANUFACTURING SAME 审中-公开
    具有单条线源的LDMOS接触器及其制造方法

    公开(公告)号：US20120037989A1

    公开(公告)日：2012-02-16

    申请号：US12857288

    申请日：2010-08-16

    申请人： Hsueh-I Huang ,  Shuo-Lun Tu ,  Ming-Tung Lee ,  Yin-Fu Huang ,  Shih-Chin Lien ,  Shyi-Yuan WU

    发明人： Hsueh-I Huang ,  Shuo-Lun Tu ,  Ming-Tung Lee ,  Yin-Fu Huang ,  Shih-Chin Lien ,  Shyi-Yuan WU

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/66689

    摘要： LDMOS devices having a single-strip contact pad in the source region, and related methods of manufacturing are disclosed. The LDMOS may comprise a first well lightly doped with a first dopant and formed into a portion of a substrate, the first well having a drain region at its surface heavily doped with the first dopant, and a second well lightly doped with a second dopant formed in another portion of the substrate, the second well having a source region at its surface comprising first portions heavily doped with the first dopant directly adjacent second portions heavily doped with the second dopant. Also, the LDMOS device may comprise a field oxide at the upper surface of the substrate between the source and drain regions, and contacting the first well but separated from the second well, and a gate formed partially over the field oxide and partially over the source region. The LDMOS may also comprise contact pads in contact with the gate, and source and drain regions, wherein the contact pad in contact with the source regions comprises a single-strip of conductive material extending across the source region.

    摘要翻译： 公开了在源区域中具有单条接触焊盘的LDMOS器件以及相关的制造方法。 LDMOS可以包括轻掺杂有第一掺杂剂并形成衬底的一部分的第一阱，第一阱在其表面上重掺杂有第一掺杂剂的漏极区，以及轻掺杂有第二掺杂剂的第二阱 在衬底的另一部分中，第二阱在其表面处具有源极区，其包括重掺杂有第一掺杂物的第一部分，其与第二掺杂剂重掺杂的第二部分直接相邻。 此外，LDMOS器件可以在源极和漏极区域之间的衬底的上表面处包括场氧化物，并且与第一阱接触但与第二阱分离，并且部分地形成在场氧化物上并部分地在源极上形成的栅极 地区。 LDMOS还可以包括与栅极接触的接触焊盘以及源极和漏极区域，其中与源极区域接触的接触焊盘包括跨越源极区域延伸的单条导电材料。

    MOS DEVICE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    MOS DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    MOS器件及其制造方法

    公开(公告)号：US20130056825A1

    公开(公告)日：2013-03-07

    申请号：US13225349

    申请日：2011-09-02

    申请人： Chien-Chung Chen ,  Ming-Tung Lee ,  Shih-Chin Lien ,  Shyi-Yuan Wu

    发明人： Chien-Chung Chen ,  Ming-Tung Lee ,  Shih-Chin Lien ,  Shyi-Yuan Wu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66492 ,  H01L21/265 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

    摘要： A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region.

    摘要翻译： 公开了形成半导体器件的半导体器件和方法，其中半导体器件在器件的源极和漏极区域中包括用于改善器件的Ron-sp和BVD特性的附加注入区域。 器件包括形成在器件衬底中分离第一和第二注入区域的沟道区域上的栅电极。 第一植入区域具有第一导电类型，并且第二植入区域具有第二导电类型。 源极扩散区域形成在第一注入区域中，并且漏极扩散区域形成在第二注入区域中。

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20120001260A1

    公开(公告)日：2012-01-05

    申请号：US12830178

    申请日：2010-07-02

    申请人： Hsueh I. Huang ,  Ming-Tung Lee ,  Shyi-Yuan Wu

    发明人： Hsueh I. Huang ,  Ming-Tung Lee ,  Shyi-Yuan Wu

    IPC分类号： H01L27/088 ,  H01L29/78

    CPC分类号： H01L29/7816 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66681

    摘要： A semiconductor device for use in a relatively high voltage application that comprises a substrate, a first n-type well region in the substrate to serve as a high voltage n-well (HVNW) for the semiconductor device, a pair of second n-type well regions in the first n-type well region, a p-type region in the first n-type well region between the second n-type well regions, a pair of conductive regions on the substrate between the second n-type well regions, and a number of n-type regions to serve as n-type buried layers (NBLs) for the semiconductor device, wherein the NBLs are located below the first n-type region and dispersed in the substrate.

    摘要翻译： 一种在相对高电压应用中使用的半导体器件，包括衬底，用作半导体器件的高电压n阱（HVNW）的衬底中的第一n型阱区，一对第二n型阱 第一n型阱区中的第一n型阱区中的p型区，第二n型阱区之间的基板上的一对导电区域， 以及用作半导体器件的n型掩埋层（NBL）的多个n型区域，其中NBL位于第一n型区域下方并分散在衬底中。

    Semiconductor devices and methods of manufacturing the same
    7.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权
    半导体器件及其制造方法

    公开(公告)号：US08354716B2

    公开(公告)日：2013-01-15

    申请号：US12830178

    申请日：2010-07-02

    申请人： Hsueh I Huang ,  Ming-Tung Lee ,  Shyi-Yuan Wu

    发明人： Hsueh I Huang ,  Ming-Tung Lee ,  Shyi-Yuan Wu

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7816 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66681

    摘要： A semiconductor device for use in a relatively high voltage application that comprises a substrate, a first n-type well region in the substrate to serve as a high voltage n-well (HVNW) for the semiconductor device, a pair of second n-type well regions in the first n-type well region, a p-type region in the first n-type well region between the second n-type well regions, a pair of conductive regions on the substrate between the second n-type well regions, and a number of n-type regions to serve as n-type buried layers (NBLs) for the semiconductor device, wherein the NBLs are located below the first n-type region and dispersed in the substrate.

    摘要翻译： 一种在相对高电压应用中使用的半导体器件，包括衬底，用作半导体器件的高电压n阱（HVNW）的衬底中的第一n型阱区，一对第二n型阱 第一n型阱区中的第一n型阱区中的p型区，第二n型阱区之间的基板上的一对导电区域， 以及用作半导体器件的n型掩埋层（NBL）的多个n型区域，其中NBL位于第一n型区域下方并分散在衬底中。

    Semiconductor bio-sensors and methods of manufacturing the same
    10.
    发明授权
    Semiconductor bio-sensors and methods of manufacturing the same 有权
    半导体生物传感器及其制造方法相同

    公开(公告)号：US08357547B2

    公开(公告)日：2013-01-22

    申请号：US13538455

    申请日：2012-06-29

    申请人： Ming-Tung Lee ,  Shih-Chin Lien ,  Chia-Huan Chang

    发明人： Ming-Tung Lee ,  Shih-Chin Lien ,  Chia-Huan Chang

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： G01N33/525 ,  G01N27/4145 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.

    摘要翻译： 制造半导体生物传感器的方法包括：提供衬底，在衬底上形成第一介电层，在第一电介质层上形成图案化的第一导电层，图案化的第一导电层包括第一部分和一对第二部分 在所述图案化的第一导电层上依次形成第二电介质层，第三电介质层和第四电介质层，在所述第四电介质层中形成空腔，形成通过所述空腔的通孔，暴露所述图案化的第一导电层的第二部分， 在所述第四电介质层上形成图案化的第二导电层，在所述图案化的第二导电层上形成钝化层，形成开口，以暴露所述图案化的第一导电层的所述第一部分上的所述第三电介质层的一部分， 通过开放。