公开(公告)号：US06383903B1

公开(公告)日：2002-05-07

申请号：US09918638

申请日：2001-08-01

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L213205

CPC分类号： H01L27/105 ,  H01L21/823418 ,  H01L21/823443 ,  H01L27/1052

摘要： This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses an oxide layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.

摘要翻译： 本发明涉及一种形成硅化物的方法，更具体地说涉及在部分区域中形成硅化物的方法。 本发明使用氧化物层作为掩模层，在逻辑电路的部分区域中形成硅化物。 硅化物形成在栅极上并且不形成在电池阵列区域中的扩散区域中。 硅化物形成在栅极和位于周边区域的扩散区域中。 本发明的方法可以使半导体器件获得较低的电阻并降低漏电缺陷。

公开(公告)号：US06548406B2

公开(公告)日：2003-04-15

申请号：US09930998

申请日：2001-08-17

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L21302

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L29/66833

摘要： A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.

摘要翻译： 公开了一种形成具有金属氧化物氮化物半导体（MONOS）存储器和混合信号电路的集成电路的方法。 本发明将诸如MONOS器件的非易失性存储器件和诸如MOS器件的逻辑器件以及PIP电容器集成到具有减少的工艺步骤的SOC器件中。

公开(公告)号：US06482738B1

公开(公告)日：2002-11-19

申请号：US09996821

申请日：2001-11-30

申请人： Ying-Tso Chen ,  Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Ying-Tso Chen ,  Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L2144

CPC分类号： H01L27/10894 ,  H01L21/28518 ,  H01L21/823443 ,  H01L21/823468 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/115 ,  H01L29/665 ,  H01L29/6656

摘要： The present invention mainly provides a method to locally form metal silicide on an integral circuit and to avoid the phenomenon of leakage current which is caused by metal silicide formed between the memory cells on the same word line. The method of present invention achieve above objectives by principally using a design rule to adequately arrange elements in proper distance. In an embodiment, in order to form metal silicide layers on an integral circuit and to avoid metal silicide formed between two neighboring memory cell on the same word line, a dielectric layer is previously formed in the spaced region between the two neighboring memory cells and is used as a mask. Thus, in a following selective etching process, a part of silicon substrate within the above spaced region can be protected and not exposed. Therefore, no metal silicide is formed in the spaced region, and the above objectives is achieved.

摘要翻译： 本发明主要提供一种在积分电路上局部形成金属硅化物的方法，并且避免由同一字线上的存储单元之间形成的金属硅化物引起的漏电流的现象。 本发明的方法通过主要使用设计规则来适当地排列适当距离的元件来达到上述目的。 在一个实施例中，为了在积分电路上形成金属硅化物层并且避免在相同字线上的两个相邻存储器单元之间形成的金属硅化物，预先在两个相邻存储器单元之间的间隔区域中形成电介质层，并且是 用作面具。 因此，在随后的选择性蚀刻工艺中，上述间隔区域内的硅衬底的一部分可被保护而不被暴露。 因此，在间隔区域中不形成金属硅化物，实现上述目的。

公开(公告)号：US06468867B1

公开(公告)日：2002-10-22

申请号：US09916267

申请日：2001-07-30

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L218234

CPC分类号： H01L27/105 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/665

摘要： This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses a nitride layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.

摘要翻译： 本发明涉及一种形成硅化物的方法，更具体地说涉及在部分区域中形成硅化物的方法。 本发明使用氮化物层作为掩模层，以在逻辑电路的部分区域中形成硅化物。 硅化物形成在栅极上并且不形成在电池阵列区域中的扩散区域中。 硅化物形成在栅极和位于周边区域的扩散区域中。 本发明的方法可以使半导体器件获得较低的电阻并降低漏电缺陷。

公开(公告)号：US06372640B1

公开(公告)日：2002-04-16

申请号：US09917645

申请日：2001-07-31

申请人： Ying-Tso Chen ,  Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Ying-Tso Chen ,  Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L2144

CPC分类号： H01L27/10894 ,  H01L21/28518 ,  H01L27/10873 ,  H01L29/665

摘要： The present invention mainly provides a method to locally form metal silicide on an integral circuit and to avoid the phenomenon of leakage current which is caused by metal silicide formed between the memory cells on the same word line. The method of the present invention achieves the above objectives by principally using a design rule to adequately arrange elements within a proper distance. In an embodiment, in order to form metal silicide layers on an integral circuit and to avoid metal silicide formed between two neighboring memory cell on the same word line, a dielectric layer is first formed in the spaced region between the two neighboring memory cells to be used as a mask. Thus, in a following selective etching process, a part of the silicon substrate within the above spaced region can be protected and not exposed. Therefore, no metal silicide is formed in the spaced region, and the above objective is achieved.

摘要翻译： 本发明主要提供一种在积分电路上局部形成金属硅化物的方法，并避免由同一字线上的存储单元之间形成的金属硅化物引起的漏电流的现象。本发明的方法实现了上述 目标主要是使用设计规则来适当地排列适当距离的元素。 在一个实施例中，为了在积分电路上形成金属硅化物层，并且避免在相同字线上的两个相邻存储器单元之间形成金属硅化物，首先在两个相邻存储器单元之间的间隔区域中形成介电层，以形成 用作面具。 因此，在随后的选择性蚀刻工艺中，上述间隔区域内的硅衬底的一部分可被保护而不被暴露。 因此，在间隔区域中不形成金属硅化物，实现上述目的。

公开(公告)号：US06448126B1

公开(公告)日：2002-09-10

申请号：US09682217

申请日：2001-08-07

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shyi-Shuh Pan

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shyi-Shuh Pan

IPC分类号： H01L218238

CPC分类号： H01L21/823418 ,  H01L21/823412

摘要： A method of forming an embedded memory integrating nitride read only memory starts by forming an ONO layer and a protective cap layer on a surface of a semiconductor substrate defined with a memory area and a periphery area. The periphery area has a first, a second and a third device area. An etching and a first ion implantation process form each bit line in the memory area. A spacer is then formed at either side of the protective cap layer and the ONO layer in the memory area, and the protective cap layer and the ONO layer are removed in the first device area. The threshold voltage for the first device area is adjusted and a first thermal oxidation process forms a buried drain oxide layer atop each bit line and a first gate oxide layer on the surface of the first device area, respectively. The protective cap layer and the ONO layer are removed from the second device area and the third device area, and a second gate oxide layer is formed in the second device area and the third device area. Finally, the protective cap layer in the memory area and the second gate oxide layer in the third device area are removed, and a third gate oxide layer is formed in the third device area.

摘要翻译： 集成氮化物只读存储器的嵌入式存储器的形成方法首先通过在由存储区域和周边区域限定的半导体衬底的表面上形成ONO层和保护覆盖层。 周边区域具有第一，第二和第三设备区域。 蚀刻和第一离子注入工艺在存储区域中形成每个位线。 然后在保护盖层和存储区域中的ONO层的任一侧形成间隔物，并且在第一装置区域中去除保护盖层和ONO层。 调整第一器件区域的阈值电压，第一热氧化工艺分别在第一器件区域的表面上的每个位线和第一栅极氧化物层的顶部形成掩埋的漏极氧化物层。 从第二设备区域和第三设备区域去除保护盖层和ONO层，并且在第二设备区域和第三设备区域中形成第二栅极氧化物层。 最后，去除存储区域中的保护盖层和第三器件区域中的第二栅极氧化物层，并且在第三器件区域中形成第三栅极氧化物层。

公开(公告)号：US06566225B2

公开(公告)日：2003-05-20

申请号：US09921580

申请日：2001-08-06

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Yu-Ping Huang

IPC分类号： H01L21336

CPC分类号： H01L21/76224

摘要： The present invention provides a formation method of a trench structure comprising forming a pad oxide layer on a substrate. A first polysilicon layer is formed on the pad oxide layer and an oxide layer is formed thereon. A second polysilicon layer is formed on the oxide layer. The partial second polysilicon layer, the oxide layer, the first polysilicon layer, and the pad oxide layer are removed to expose the partial substrate. The second polysilicon layer and the partial substrate are etched for forming the trench structure in the substrate. An etched depth of the trench structure is well controlled by the etched thickness of the second polysilicon layer.

摘要翻译： 本发明提供一种沟槽结构的形成方法，包括在衬底上形成衬垫氧化物层。 在衬垫氧化物层上形成第一多晶硅层，在其上形成氧化物层。 在氧化物层上形成第二多晶硅层。 去除部分第二多晶硅层，氧化物层，第一多晶硅层和衬垫氧化物层以暴露部分衬底。 蚀刻第二多晶硅层和部分衬底以在衬底中形成沟槽结构。 沟槽结构的蚀刻深度由第二多晶硅层的蚀刻厚度很好地控制。

公开(公告)号：US06599793B2

公开(公告)日：2003-07-29

申请号：US09901888

申请日：2001-05-31

申请人： Ming-Hung Chou ,  Jui-Lin Lu ,  Chong-Jen Huang ,  Shou-Wei Hwang ,  Hsin-Huei Chen

发明人： Ming-Hung Chou ,  Jui-Lin Lu ,  Chong-Jen Huang ,  Shou-Wei Hwang ,  Hsin-Huei Chen

IPC分类号： H01L218238

CPC分类号： H01L21/823835 ,  H01L21/76202 ,  H01L21/76224

摘要： The present invention provides a memory array fabricated by complementary metal-oxide-semiconductor salicide process. The memory array comprises a semiconductor substrate. Multitudes of first isolation devices are aligned in the semiconductor substrate and second isolation devices aligned on the semiconductor substrate. The alignment of the second isolation devices is parallel to one of the first isolation devices. Some polysilicon lines are on the second isolation devices therefor have null memory function. A conductive structure is below a surface of the semiconductor substrate. The conductive structure is located between the first isolation devices. A conductive contact is on the conductive structure. The correspondence of the first isolation devices and the polysilicon lines can prevent the conductive structures from short effect.

公开(公告)号：US07923770B2

公开(公告)日：2011-04-12

申请号：US12140064

申请日：2008-06-16

申请人： Chih-Lin Chen ,  Kuang-Wen Liu ,  Hsin-Huei Chen

发明人： Chih-Lin Chen ,  Kuang-Wen Liu ,  Hsin-Huei Chen

IPC分类号： H01L29/788

CPC分类号： H01L21/28282 ,  H01L29/4234 ,  H01L29/792

摘要： A method of fabricating memory devices is provided. First, a charge storage structure including a gate dielectric structure is formed on the substrate in sequence to form a charge trapping layer. Then, a gate conductive layer is formed above the charge storage structure. Afterwards, the gate conductive layer and at least a part of the charge storage structure are patterned. The cross section of the patterned charge storage structure is then become a trapezoid or a trapezoid analogue, which has the shorter side near the gate conductive layer and the longer side near the substrate.

摘要翻译： 提供一种制造存储器件的方法。 首先，依次在基板上形成包括栅介电结构的电荷存储结构，以形成电荷捕获层。 然后，在电荷存储结构的上方形成栅极导电层。 之后，栅极导电层和电荷存储结构的至少一部分被图案化。 图案化电荷存储结构的横截面然后变成梯形或梯形模拟物，其在栅极导电层附近具有较短的一侧，在衬底附近具有较长的一侧。

公开(公告)号：US20070117353A1

公开(公告)日：2007-05-24

申请号：US11625177

申请日：2007-01-19

申请人： Chih Hao Wang ,  Hsin-Huei Chen ,  Chong-Jen Huang ,  Kuang-Wen Liu ,  Jia-Rong Chiou ,  Chong-Mu Chen

发明人： Chih Hao Wang ,  Hsin-Huei Chen ,  Chong-Jen Huang ,  Kuang-Wen Liu ,  Jia-Rong Chiou ,  Chong-Mu Chen

IPC分类号： H01L29/94 ,  H01L21/326

CPC分类号： H01L21/022 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L21/3144 ,  H01L29/66833 ,  Y10S438/954

摘要： A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures. Exposing the patterned silicon nitride to the oxygen radical during the RTO according to the invention significantly reduces the processing time, and reduces the thermal budget. Moreover, because according to the invention the upper surface and the sidewalls of the silicon nitride layer are covered by the top oxide layer, the silicon nitride is not exposed during a subsequent cleaning process. As a result of increased contact area between the polysilicon gate and the top oxide layer, the coupling ratio of the gate is increased.

摘要翻译： 通过在具有存储区域和逻辑器件区域的衬底上提供第一氧化硅层和氮化硅层来形成具有氧化硅/氮化硅/氧化硅（“ONO”）结构的半导体器件; 图案化第一氧化硅层和氮化硅层以限定部分完成的ONO堆叠的底部氧化物和氮化硅部分并且暴露逻辑器件区域中的衬底; 在自由基氧化剂的存在下进行快速热退火工艺，以在氮化硅层的暴露表面和衬底上的栅氧化层上同时形成第二氧化硅层; 以及在完成的ONO堆叠和栅极氧化物上沉积导电层。 本发明用于制造例如具有外围逻辑器件的存储器件和包括ONO结构的存储器单元。 根据本发明，在RTO期间将图案化的氮化硅暴露于氧自由基显着减少了处理时间，并降低了热预算。 此外，由于根据本发明，氮化硅层的上表面和侧壁被顶部氧化物层覆盖，所以在随后的清洁过程中氮化硅不暴露。 由于多晶硅栅极和顶部氧化物层之间的接触面积增加，栅极的耦合比增加。