公开(公告)号：US06586146B2

公开(公告)日：2003-07-01

申请号：US09945068

申请日：2001-08-31

申请人： Kun-Yuan Chang ,  Wang-Hsiang Ho ,  Yu-Ping Huang ,  Li-Dar Tsai ,  Chung-Yung Wu

发明人： Kun-Yuan Chang ,  Wang-Hsiang Ho ,  Yu-Ping Huang ,  Li-Dar Tsai ,  Chung-Yung Wu

IPC分类号： G03F900

CPC分类号： G03F7/70558 ,  G03F7/70625

摘要： A method of figuring an exposure energy. A required exposure energy is calculated according to a critical dimension (CD) of an exposing layer. A first CD deviation is obtained from a layer before the exposing layer. From the first CD deviation, a first energy compensation is calculated. Whether the deviation of photoresist sensitivity of two sequential batches is less than 1% is checked. If the deviation of photoresist sensitivity of two sequential batches is less than 1%, a sum of the required exposure energy and the first energy compensation is the exposure energy applied to the exposing layer. Otherwise, a second CD deviation is commutated according to the deviation of photoresist sensitivity of two sequential batches. A second energy compensation is then obtained from the second CD deviation, and a sum of the required exposure energy and the first/second energy compensation is the exposure energy applied to the exposing layer.

摘要翻译： 计算曝光能量的方法。 根据暴露层的临界尺寸（CD）计算所需的曝光能量。 从暴露层之前的层获得第一CD偏差。 从第一个CD偏差，计算第一个能量补偿。 检查两个连续批次的光敏感性的偏差是否小于1％。 如果两个连续批次的光致抗敏剂的偏差小于1％，则所需的曝光能量和第一能量补偿之和是施加到曝光层的曝光能量。 否则，根据两个连续批次的光致抗敏剂的偏差，第二CD偏差被换算。 然后从第二CD偏差获得第二能量补偿，并且所需曝光能量和第一/第二能量补偿之和是施加到曝光层的曝光能量。

公开(公告)号：US06383903B1

公开(公告)日：2002-05-07

申请号：US09918638

申请日：2001-08-01

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L213205

CPC分类号： H01L27/105 ,  H01L21/823418 ,  H01L21/823443 ,  H01L27/1052

摘要： This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses an oxide layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.

摘要翻译： 本发明涉及一种形成硅化物的方法，更具体地说涉及在部分区域中形成硅化物的方法。 本发明使用氧化物层作为掩模层，在逻辑电路的部分区域中形成硅化物。 硅化物形成在栅极上并且不形成在电池阵列区域中的扩散区域中。 硅化物形成在栅极和位于周边区域的扩散区域中。 本发明的方法可以使半导体器件获得较低的电阻并降低漏电缺陷。

公开(公告)号：US06355539B1

公开(公告)日：2002-03-12

申请号：US09849245

申请日：2001-05-07

申请人： Erh-Kun Lai ,  Shou-Wei Huang ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Shou-Wei Huang ,  Yu-Ping Huang

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： A method for forming a shallow trench isolation is disclosed. The method avoids using any silicon nitride material to prevent the kooi effect and use spacers to protect the corner portions of the STI. A conductive layer is used to replace the conventional used silicon nitride layer in the formation of conventional STI regions. The invention also uses a dielectric layer comprising a pad oxide layer as a sacrificial oxide layer so that an additional sacrificial oxide layer is no longer needed. The conductive layer will be oxidized together with the substrate in the formation of the gate oxide layer so that the isolation quality will not be degraded.

摘要翻译： 公开了一种用于形成浅沟槽隔离的方法。 该方法避免使用任何氮化硅材料来防止kooi效应并使用间隔物来保护STI的拐角部分。 在传统的STI区域的形成中，使用导电层代替常规使用的氮化硅层。 本发明还使用包括衬垫氧化物层作为牺牲氧化物层的电介质层，使得不再需要额外的牺牲氧化物层。 在形成栅极氧化物层时，导电层将与衬底一起被氧化，使得隔离质量不会降低。

公开(公告)号：US08957660B2

公开(公告)日：2015-02-17

申请号：US13610792

申请日：2012-09-11

申请人： Ke-Horng Chen ,  Yueh-Lung Kuo ,  Chih-Heng Su ,  Yi-Ping Su ,  Yu-Ping Huang ,  Yu-Huei Lee

发明人： Ke-Horng Chen ,  Yueh-Lung Kuo ,  Chih-Heng Su ,  Yi-Ping Su ,  Yu-Ping Huang ,  Yu-Huei Lee

IPC分类号： G05F1/00

CPC分类号： H02M1/084 ,  H02M3/1584 ,  H02M2001/0025 ,  H02M2003/1586

摘要： The present invention discloses a current balance circuit for a multiphase DC-DC converter. The current balance circuit comprises a current error calculation circuit, for generating a plurality of current balance signals indicating imbalance levels of a plurality of inductor currents of a plurality of channels of the multiphase DC-DC converter according to a plurality of current sensing signals of the plurality of channels, a time shift circuit, for adjusting pulse widths of a plurality of clock signals according to the plurality of current balance signals, and a ramp generator, for deciding shift levels of a plurality of ramp signals according to the plurality of clock signals.

摘要翻译： 本发明公开了一种用于多相DC-DC转换器的电流平衡电路。 电流平衡电路包括电流误差计算电路，用于根据多个电流感测信号产生指示多相DC-DC转换器的多个通道的多个电感电流的不平衡电平的多个电流平衡信号 多个通道，用于根据多个电流平衡信号调整多个时钟信号的脉冲宽度的时移电路和用于根据多个时钟信号确定多个斜坡信号的移位电平的斜坡发生器 。

公开(公告)号：US20130293203A1

公开(公告)日：2013-11-07

申请号：US13610792

申请日：2012-09-11

申请人： Ke-Horng Chen ,  Yueh-Lung Kuo ,  Chih-Heng Su ,  Yi-Ping Su ,  Yu-Ping Huang ,  Yu-Huei Lee

发明人： Ke-Horng Chen ,  Yueh-Lung Kuo ,  Chih-Heng Su ,  Yi-Ping Su ,  Yu-Ping Huang ,  Yu-Huei Lee

IPC分类号： G05F1/46

CPC分类号： H02M1/084 ,  H02M3/1584 ,  H02M2001/0025 ,  H02M2003/1586

摘要： The present invention discloses a current balance circuit for a multiphase DC-DC converter. The current balance circuit comprises a current error calculation circuit, for generating a plurality of current balance signals indicating imbalance levels of a plurality of inductor currents of a plurality of channels of the multiphase DC-DC converter according to a plurality of current sensing signals of the plurality of channels, a time shift circuit, for adjusting pulse widths of a plurality of clock signals according to the plurality of current balance signals, and a ramp generator, for deciding shift levels of a plurality of ramp signals according to the plurality of clock signals.

摘要翻译： 本发明公开了一种用于多相DC-DC转换器的电流平衡电路。 电流平衡电路包括电流误差计算电路，用于根据多个电流感测信号产生指示多相DC-DC转换器的多个通道的多个电感电流的不平衡电平的多个电流平衡信号 多个通道，用于根据多个电流平衡信号调整多个时钟信号的脉冲宽度的时移电路和用于根据多个时钟信号确定多个斜坡信号的移位电平的斜坡发生器 。

公开(公告)号：US06482738B1

公开(公告)日：2002-11-19

申请号：US09996821

申请日：2001-11-30

申请人： Ying-Tso Chen ,  Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Ying-Tso Chen ,  Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L2144

CPC分类号： H01L27/10894 ,  H01L21/28518 ,  H01L21/823443 ,  H01L21/823468 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/115 ,  H01L29/665 ,  H01L29/6656

摘要： The present invention mainly provides a method to locally form metal silicide on an integral circuit and to avoid the phenomenon of leakage current which is caused by metal silicide formed between the memory cells on the same word line. The method of present invention achieve above objectives by principally using a design rule to adequately arrange elements in proper distance. In an embodiment, in order to form metal silicide layers on an integral circuit and to avoid metal silicide formed between two neighboring memory cell on the same word line, a dielectric layer is previously formed in the spaced region between the two neighboring memory cells and is used as a mask. Thus, in a following selective etching process, a part of silicon substrate within the above spaced region can be protected and not exposed. Therefore, no metal silicide is formed in the spaced region, and the above objectives is achieved.

摘要翻译： 本发明主要提供一种在积分电路上局部形成金属硅化物的方法，并且避免由同一字线上的存储单元之间形成的金属硅化物引起的漏电流的现象。 本发明的方法通过主要使用设计规则来适当地排列适当距离的元件来达到上述目的。 在一个实施例中，为了在积分电路上形成金属硅化物层并且避免在相同字线上的两个相邻存储器单元之间形成的金属硅化物，预先在两个相邻存储器单元之间的间隔区域中形成电介质层，并且是 用作面具。 因此，在随后的选择性蚀刻工艺中，上述间隔区域内的硅衬底的一部分可被保护而不被暴露。 因此，在间隔区域中不形成金属硅化物，实现上述目的。

公开(公告)号：US06468867B1

公开(公告)日：2002-10-22

申请号：US09916267

申请日：2001-07-30

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L218234

CPC分类号： H01L27/105 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/665

摘要： This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses a nitride layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.

摘要翻译： 本发明涉及一种形成硅化物的方法，更具体地说涉及在部分区域中形成硅化物的方法。 本发明使用氮化物层作为掩模层，以在逻辑电路的部分区域中形成硅化物。 硅化物形成在栅极上并且不形成在电池阵列区域中的扩散区域中。 硅化物形成在栅极和位于周边区域的扩散区域中。 本发明的方法可以使半导体器件获得较低的电阻并降低漏电缺陷。

公开(公告)号：US06387750B1

公开(公告)日：2002-05-14

申请号：US09895389

申请日：2001-07-02

申请人： Erh-Kun Lai ,  Shou-Wei Hwang ,  Jiann-Jen Chiou ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Shou-Wei Hwang ,  Jiann-Jen Chiou ,  Yu-Ping Huang

IPC分类号： H01L218242

CPC分类号： H01L28/92 ,  H01L27/0805 ,  H01L29/66181

摘要： A method of forming a metal-insulator-metal (MIM) capacitor is disclosed. The method provides a three dimensional MIM capacitor having upgraded capacitance. A plurality of trenches are formed within the MIM capacitor to increase the charge storage area of the MIM capacitor without occupying additional planar area thereby upgrade the capacitance of the MIM capacitor and the integration.

摘要翻译： 公开了一种形成金属 - 绝缘体 - 金属（MIM）电容器的方法。 该方法提供具有升级电容的三维MIM电容器。 在MIM电容器内形成多个沟槽，以增加MIM电容器的电荷存储区域，而不占用额外的平面区域，从而升高MIM电容器的电容和集成度。

公开(公告)号：US06372640B1

公开(公告)日：2002-04-16

申请号：US09917645

申请日：2001-07-31

申请人： Ying-Tso Chen ,  Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Ying-Tso Chen ,  Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L2144

CPC分类号： H01L27/10894 ,  H01L21/28518 ,  H01L27/10873 ,  H01L29/665

摘要： The present invention mainly provides a method to locally form metal silicide on an integral circuit and to avoid the phenomenon of leakage current which is caused by metal silicide formed between the memory cells on the same word line. The method of the present invention achieves the above objectives by principally using a design rule to adequately arrange elements within a proper distance. In an embodiment, in order to form metal silicide layers on an integral circuit and to avoid metal silicide formed between two neighboring memory cell on the same word line, a dielectric layer is first formed in the spaced region between the two neighboring memory cells to be used as a mask. Thus, in a following selective etching process, a part of the silicon substrate within the above spaced region can be protected and not exposed. Therefore, no metal silicide is formed in the spaced region, and the above objective is achieved.

摘要翻译： 本发明主要提供一种在积分电路上局部形成金属硅化物的方法，并避免由同一字线上的存储单元之间形成的金属硅化物引起的漏电流的现象。本发明的方法实现了上述 目标主要是使用设计规则来适当地排列适当距离的元素。 在一个实施例中，为了在积分电路上形成金属硅化物层，并且避免在相同字线上的两个相邻存储器单元之间形成金属硅化物，首先在两个相邻存储器单元之间的间隔区域中形成介电层，以形成 用作面具。 因此，在随后的选择性蚀刻工艺中，上述间隔区域内的硅衬底的一部分可被保护而不被暴露。 因此，在间隔区域中不形成金属硅化物，实现上述目的。

公开(公告)号：US06566225B2

公开(公告)日：2003-05-20

申请号：US09921580

申请日：2001-08-06

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Yu-Ping Huang

IPC分类号： H01L21336

CPC分类号： H01L21/76224

摘要： The present invention provides a formation method of a trench structure comprising forming a pad oxide layer on a substrate. A first polysilicon layer is formed on the pad oxide layer and an oxide layer is formed thereon. A second polysilicon layer is formed on the oxide layer. The partial second polysilicon layer, the oxide layer, the first polysilicon layer, and the pad oxide layer are removed to expose the partial substrate. The second polysilicon layer and the partial substrate are etched for forming the trench structure in the substrate. An etched depth of the trench structure is well controlled by the etched thickness of the second polysilicon layer.

摘要翻译： 本发明提供一种沟槽结构的形成方法，包括在衬底上形成衬垫氧化物层。 在衬垫氧化物层上形成第一多晶硅层，在其上形成氧化物层。 在氧化物层上形成第二多晶硅层。 去除部分第二多晶硅层，氧化物层，第一多晶硅层和衬垫氧化物层以暴露部分衬底。 蚀刻第二多晶硅层和部分衬底以在衬底中形成沟槽结构。 沟槽结构的蚀刻深度由第二多晶硅层的蚀刻厚度很好地控制。