公开(公告)号：US5516707A

公开(公告)日：1996-05-14

申请号：US489525

申请日：1995-06-12

申请人： Ying-Tsong Loh ,  Lily Ding ,  Edward D. Nowak

发明人： Ying-Tsong Loh ,  Lily Ding ,  Edward D. Nowak

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/51

CPC分类号： H01L29/518 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28176 ,  H01L29/6659 ,  H01L21/28194

摘要： A transistor is formed which has improved hot carrier immunity. On a substrate, between two source/drain regions, a gate region is formed over a dielectric region. An implant is used to dope the source/drain regions. After doping the source/drain regions, a tilted angle nitrogen implant is performed to implant nitrogen into areas of the dielectric region overlaying the drain/source regions of the transistor. The tilted angle nitrogen implant may be performed before or after forming spacer regions on sides of the gate region.

摘要翻译： 形成了具有改善的热载体免疫性的晶体管。 在衬底上，在两个源极/漏极区之间，在电介质区域上形成栅极区。 植入物用于掺杂源极/漏极区域。 在掺杂源极/漏极区域之后，执行倾斜角度的氮注入以将氮注入到覆盖晶体管的漏极/源极区域的介电区域的区域中。 可以在形成在栅极区域的侧面上的间隔区域之前或之后进行倾斜角度的氮注入。

公开(公告)号：US5759901A

公开(公告)日：1998-06-02

申请号：US905234

申请日：1997-08-01

申请人： Ying-Tsong Loh ,  Lily Ding

发明人： Ying-Tsong Loh ,  Lily Ding

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L21/28061

摘要： A technique for forming a high-performance sub-half micron MOS transistor is disclosed which has improved short channel characteristics without degradation of device performance. The transistor comprises a semiconductor substrate, a gate electrode, graded source and drain impurity regions, a first set of gate sidewall spacers, and a second set of gate sidewall spacers. The graded source and drain impurity regions comprise a relatively linear continuum of doped regions, ranging from lightly doped (LDD) regions, to moderately doped (MDD) regions, to heavily doped regions. Additionally, the transistor may include a punch through barrier region located within the substrate under the gate electrode. With these features, the transistor of the present invention allows for more precise control of conduction channel length without degradation of either (1) body factor and current drive, and/or (2) junction leakage, and without compromising hot carrier immunity.

摘要翻译： 公开了一种用于形成高性能半微米MOS晶体管的技术，其具有改善的短沟道特性，而不会降低器件性能。 晶体管包括半导体衬底，栅电极，渐变源极和漏极杂质区域，第一组栅极侧壁间隔物和第二组栅极侧壁间隔物。 分级的源极和漏极杂质区域包括从轻掺杂（LDD）区域到中等掺杂（MDD）区域到掺杂区域的相对线性连续的掺杂区域。 另外，晶体管可以包括位于栅电极下方的衬底内的穿通阻挡区域。 利用这些特征，本发明的晶体管允许对传导通道长度进行更精确的控制，而不会降低（1）体因子和电流驱动，和/或（2）结漏电，并且不影响热载体的抗扰性。

公开(公告)号：US5700717A

公开(公告)日：1997-12-23

申请号：US557659

申请日：1995-11-13

申请人： Edward D. Nowak ,  Ying-Tsong Loh ,  Lily Ding

发明人： Edward D. Nowak ,  Ying-Tsong Loh ,  Lily Ding

IPC分类号： H01L21/285 ,  A01L21/28

CPC分类号： H01L21/28512

摘要： A system and method for reducing the contact resistance associated with tungsten plug contacts to P-doped diffusion regions of a semiconductor device. Before or during the formation of the tungsten plug contacts, a high energy, low dosage of an N-dopant or neutral species such as silicon or germanium is implanted into the P-doped diffusion regions of the semiconductor device. The implantation causes lattice damage within the P-doped diffusion regions, enhancing diffusion of the P-dopant within the P-doped diffusion regions. This results in the P-dopant diffusing toward the contact, replacing dopant lost to segregation into the contact metalization, and thus reducing the contact resistance.

摘要翻译： 一种用于将与钨插头接触相关联的接触电阻降低到半导体器件的P掺杂扩散区域的系统和方法。 在形成钨插头接触之前或期间，将N掺杂剂或中性物质如硅或锗的高能量，低剂量注入到半导体器件的P掺杂扩散区域中。 该注入在P掺杂扩散区域内引起晶格损伤，增强P掺杂扩散区内P掺杂剂的扩散。 这导致P型掺杂剂朝向接触物扩散，代替掺杂物损失到偏析到接触金属化中，从而降低接触电阻。

公开(公告)号：US5288652A

公开(公告)日：1994-02-22

申请号：US993229

申请日：1992-12-18

申请人： Chung S. Wang ,  Ying-Tsong Loh ,  Edward D. Nowak

发明人： Chung S. Wang ,  Ying-Tsong Loh ,  Edward D. Nowak

IPC分类号： H01L21/8249 ,  H01L21/265 ,  H01L29/70

CPC分类号： H01L21/8249 ,  Y10S438/944

摘要： A bipolar transistor is fabricated in a CMOS-compatible process with a laterally graded emitter structure that is fabricated in a "top-down" implant process. The laterally graded emitter decreases electric field intensities in the emitter-base junction under reverse bias, thus reducing hot carrier generation and improving emitter-base junction breakdown voltage. High current gain is further maintained by establishing sharply defined emitter-base junctions. During fabrication a blocking layer and overlying cap layer are formed in an inverted "T" shape over a desired emitter window region. Lateral projection of the cap ledges are used to define the laterally graded emitter width, while the distance separating the cap ledges defines the width of the central emitter region. The central emitter region is implanted and driven-in to a desired depth, after which the protective cap is removed. The entire emitter window region is then implanted with a like polarity dopant of lesser dosage, which dopant is then driven-in to form laterally graded emitter junctions of a desired depth. A BiCMOS integrated circuit may be fabricated with bipolar transistors of either polarity and with MOS transistors of either polarity, using substantially the same process steps. The resultant MOS devices have lightly doped drain regions to enhance MOS hot carrier performance.

摘要翻译： 双极晶体管以CMOS兼容工艺制造，具有以“自顶向下”注入工艺制造的横向渐变发射极结构。 横向渐变发射极在反向偏压下降低发射极 - 基极结中的电场强度，从而减少热载流子的产生并改善发射极 - 基极结击穿电压。 通过建立清晰的发射极 - 基极结，进一步维持高电流增益。 在制造期间，在期望的发射器窗口区域上以倒置的“T”形状形成阻挡层和覆盖覆盖层。 盖凸缘的横向投影用于限定横向渐变发射器宽度，而分隔盖凸缘的距离限定了中心发射极区域的宽度。 将中心发射极区域植入并驱动到期望的深度，之后去除保护盖。 然后用较小剂量的类似极性掺杂剂注入整个发射极窗口区域，然后将该掺杂剂驱入以形成期望深度的横向渐变的发射极结。 可以使用基本上相同的工艺步骤，制造具有任一极性的双极晶体管和任一极性的MOS晶体管的BiCMOS集成电路。 所得的MOS器件具有轻掺杂漏极区以增强MOS热载体性能。

公开(公告)号：US5793094A

公开(公告)日：1998-08-11

申请号：US579780

申请日：1995-12-28

申请人： Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh ,  Walter D. Parmantie

发明人： Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh ,  Walter D. Parmantie

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： A method for substantially reducing variations in a programming voltage of an anti-fuse structure formed on an integrated circuit wafer. The anti-fuse structure has a metal-one layer, an anti-fuse layer disposed above the metal-one layer, a oxide layer disposed above the anti-fuse layer, and a via hole in the oxide layer through to the anti-fuse layer for receiving a deposition of a metal-two material. The method includes the step of rendering a selected anti-fuse area susceptible to fuse link formation by reducing a resistivity of the selected anti-fuse area to diffusion of atoms from one of the metal-one layer and the metal-two layer when a programming voltage is applied between the metal one layer and the metal two layer. The selected anti-fuse area is located in the anti-fuse layer and substantially adjacent to and outside of an anti-fuse area directly below the via hole. The method further includes the step of depositing the metal-two material into the via hole.

摘要翻译： 一种用于基本上减少在集成电路晶片上形成的抗熔丝结构的编程电压的变化的方法。 反熔丝结构具有金属一层，设置在金属一层上方的抗熔丝层，设置在抗熔融层上方的氧化物层，以及氧化物层中的通孔到反熔丝 用于接收金属二材料的沉积的层。 该方法包括以下步骤：当编程时，通过降低所选择的反熔丝区域与金属层和金属二层中的一个的原子的扩散，使选择的抗熔丝区域易于熔融链接形成 在金属一层和金属两层之间施加电压。 所选择的反熔丝区域位于反熔丝层中，并且基本上邻近通孔正下方的反熔丝区域的外部。 该方法还包括将金属二材料沉积到通孔中的步骤。

公开(公告)号：US5789795A

公开(公告)日：1998-08-04

申请号：US579824

申请日：1995-12-28

申请人： Ivan Sanchez ,  Yu-Pin Han ,  Miguel A. Delgado ,  Ying-Tsong Loh

发明人： Ivan Sanchez ,  Yu-Pin Han ,  Miguel A. Delgado ,  Ying-Tsong Loh

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： An integrated circuit having a semiconductor substrate and an anti-fuse structure formed on the semiconductor substrate. The anti-fuse structure includes a metal-one layer and an anti-fuse layer disposed above the metal-one layer. The anti-fuse layer has a first resistance value when the anti-fuse structure is unprogrammed and a second resistance value lower than the first resistance value when the anti-fuse structure is programmed. There is further provided an etch stop layer disposed above the anti-fuse layer, and an inter-metal oxide layer disposed above the etch stop layer with the inter-metal oxide layer has a via formed therein. Additionally, there is further provided a metal-two layer disposed above the inter-metal oxide layer. In this structure, a portion of the metal-two layer is in electrical contact with the anti-fuse layer through the via in the inter-metal oxide layer.

摘要翻译： 具有形成在半导体衬底上的半导体衬底和抗熔丝结构的集成电路。 反熔丝结构包括金属一层和设置在金属一层上方的抗熔丝层。 当抗熔丝结构未被编程时，抗熔丝层具有第一电阻值，并且当编程防熔丝结构时，抗熔丝层具有低于第一电阻值的第二电阻值。 还提供了设置在反熔丝层上方的蚀刻停止层，并且设置在蚀刻停止层上方的金属间氧化物层与金属间氧化物层在其中形成通孔。 此外，还提供了设置在金属间氧化物层上方的金属二层。 在该结构中，金属二层的一部分通过金属间氧化物层中的通孔与抗熔融层电接触。

公开(公告)号：US5753540A

公开(公告)日：1998-05-19

申请号：US699867

申请日：1996-08-20

申请人： Koucheng Wu ,  Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh

发明人： Koucheng Wu ,  Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh

IPC分类号： H01L23/525 ,  H01L21/82

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

摘要： Disclosed is a method for programming an antifuse structure. The antifuse structure is programmed by applying an alternating current having alternating current pulses between a bottom and a top electrode to generate a conduction path through an antifuse material sandwiched between the electrodes. The conduction path is formed incrementally due to an electron flow produced as a result of each alternating current pulse thereby defining the conduction path at a substantially centered portion of the antifuse material.

摘要翻译： 公开了一种用于编程反熔丝结构的方法。 反熔丝结构通过在底部和顶部电极之间施加具有交流电脉冲的交流电来编程，以产生穿过夹在电极之间的反熔丝的导电路径。 由于由于每个交流脉冲而产生的电子流，传导路径增量地形成，从而在反熔丝材料的基本中心部分处限定导电路径。

公开(公告)号：US5783467A

公开(公告)日：1998-07-21

申请号：US582844

申请日：1995-12-29

申请人： Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

发明人： Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/82

CPC分类号： H01L27/11206 ,  H01L27/112

摘要： An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.

摘要翻译： 反熔丝结构包括第一电极，在第一电极上方的增强非晶硅层，以及增强非晶硅层上的第二电极。 通过将中性物质和掺杂剂物质的离子注入到非晶硅的沉积层中形成增强非晶硅层，使得反熔丝结构将在编程状态下具有稳定的导电链路，并且使得其将被 在非编程状态下较不易于断态泄漏。 制造反熔丝结构的方法包括形成下电极，在下电极上沉积非晶硅层，将中性物质和掺杂剂物质离子注入到非晶硅层中，以及在非晶硅层上形成上电极。

公开(公告)号：US5821558A

公开(公告)日：1998-10-13

申请号：US792791

申请日：1997-02-03

申请人： Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

发明人： Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L29/04 ,  H01L27/02

CPC分类号： H01L27/11206 ,  H01L27/112

摘要： An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.

摘要翻译： 反熔丝结构包括第一电极，在第一电极上方的增强非晶硅层，以及增强非晶硅层上的第二电极。 通过将中性物质和掺杂剂物质的离子注入到非晶硅的沉积层中形成增强非晶硅层，使得反熔丝结构将在编程状态下具有稳定的导电链路，并且使得其将被 在非编程状态下较不易于断态泄漏。 制造反熔丝结构的方法包括形成下电极，在下电极上沉积非晶硅层，将中性物质和掺杂剂物质离子注入到非晶硅层中，以及在非晶硅层上形成上电极。

公开(公告)号：US5793640A

公开(公告)日：1998-08-11

申请号：US773171

申请日：1996-12-26

申请人： Koucheng Wu ,  Yu-Pin Han ,  Ying-Tsong Loh

发明人： Koucheng Wu ,  Yu-Pin Han ,  Ying-Tsong Loh

IPC分类号： G01R27/26 ,  G01R27/00

CPC分类号： G01R27/2605

摘要： A computer-aided method and system are provided for obtaining a measurement of the capacitance value of a device under test (DUT). The complex impedance of a device under test (DUT) is measured at two nearby frequencies using an RLC meter. The two complex impedance values are then stored in a computer readable medium. The DUT is modeled by a programmed computer as a four element RLC model circuit including a resistor and inductor in series with a parallel RC circuit having a single capacitor which represents the capacitance of the DUT. Four equations which describe the electrical characteristics of the four element RLC model circuit are stored in a computer readable medium. The four measured values of complex impedance are substituted by the computer into the four stored equations. Values are obtained for the four individual RLC circuit elements by solving the four equations. The four unknown values are obtained by use of an optimization routine and then stored to a computer readable medium. The value capacitor element representing the capacitance of the DUT is then displayed.

摘要翻译： 提供了一种计算机辅助方法和系统，用于获得待测器件（DUT）的电容值的测量。 被测设备（DUT）的复阻抗使用RLC仪在两个附近的频率下测量。 然后将两个复阻抗值存储在计算机可读介质中。 DUT被编程的计算机建模为四元件RLC模型电路，其包括与表示DUT的电容的单个电容器的并联RC电路串联的电阻器和电感器。 描述四元素RLC模型电路的电特性的四个等式被存储在计算机可读介质中。 复阻抗的四个测量值被计算机代入四个存储的方程。 通过求解四个等式获得四个单独的RLC电路元件的值。 通过使用优化例程获得四个未知值，然后将其存储到计算机可读介质中。 然后显示表示DUT的电容的值电容器元件。