公开(公告)号：US06407008B1

公开(公告)日：2002-06-18

申请号：US09564786

申请日：2000-05-05

申请人： Yingbo Jia ,  Ohm-Guo Pan ,  Long-Ching Wang ,  Jeong Yeol Choi ,  Guo-Qiang (Patrick) Lo ,  Shih-Ked Lee

发明人： Yingbo Jia ,  Ohm-Guo Pan ,  Long-Ching Wang ,  Jeong Yeol Choi ,  Guo-Qiang (Patrick) Lo ,  Shih-Ked Lee

IPC分类号： H01L21314

CPC分类号： H01L21/28202 ,  C23C8/10 ,  C30B29/06 ,  C30B33/005 ,  H01L21/3144 ,  H01L21/31658 ,  H01L29/518

摘要： Methods for forming nitrided oxides in semiconductor devices by rapid thermal oxidation, in which a semiconductor substrate having an exposed silicon surface is placed into a thermal process chamber. Then, an ambient gas comprising N2O and an inert gas such as argon or N2 is introduced into the process chamber. Next, the silicon surface is heated to a predefined process temperature, thereby oxidizing at least a portion of the silicon surface. Finally, the semiconductor substrate is cooled. An ultra-thin oxide layer with uniform oxide characteristics, such as more boron penetration resistance, good oxide composition and thickness uniformity, increased charge to breakdown voltage in the oxide layer, can be formed.

摘要翻译： 通过快速热氧化在半导体器件中形成氮化氧化物的方法，其中具有暴露的硅表面的半导体衬底被放置在热处理室中。 然后，将包含N 2 O和惰性气体如氩气或N 2的环境气体引入处理室。 接下来，将硅表面加热到预定的工艺温度，从而氧化硅表面的至少一部分。 最后，冷却半导体衬底。 可以形成具有均匀氧化特性的超薄氧化物层，例如更多的硼渗透阻力，良好的氧化物组成和厚度均匀性，增加氧化物层中的电荷到击穿电压。

公开(公告)号：US20110140254A1

公开(公告)日：2011-06-16

申请号：US12638827

申请日：2009-12-15

申请人： Chen Lung Tsai ,  Long-Ching Wang ,  Tze-Pin Lin

发明人： Chen Lung Tsai ,  Long-Ching Wang ,  Tze-Pin Lin

IPC分类号： H01L23/495 ,  H01L21/78

CPC分类号： H01L23/5389 ,  H01L21/4832 ,  H01L21/568 ,  H01L23/495 ,  H01L23/49548 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A packaged semiconductor die has a preformed lead frame with a central recessed portion, and a plurality of conductive leads. An integrated circuit die has a top surface and a bottom surface opposite thereto, with the top surface having a plurality of bonding pads for electrical connection to the die. The die is positioned in the central recessed portion with the top surface having the bonding pads facing upward, and the bottom surface in contact with the recessed portion. Each of the leads has a top portion and a bottom portion. The leads are spaced apart and insulated from the central recessed portion. A conductive layer is deposited on the top surface of the die and the top portion of the leads and is patterned to electrically connect certain of the bonding pads of the die to certain of the conductive leads. An insulator covers the conductive layer. The present invention also relates to a method of packaging such an integrated circuit die.

摘要翻译： 封装的半导体管芯具有中心凹部的预成形引线框架和多个导电引线。 集成电路管芯具有与其相对的顶表面和底表面，其顶表面具有用于与管芯电连接的多个接合焊盘。 模具位于中央凹部中，顶表面具有面向上的接合焊盘，并且底表面与凹部接触。 每个引线具有顶部和底部。 引线间隔开并与中心凹部绝缘。 导电层沉积在管芯的顶表面和引线的顶部，并被图案化以将管芯的某些焊盘电连接到某些导电引线。 绝缘体覆盖导电层。 本发明还涉及一种封装这种集成电路管芯的方法。

公开(公告)号：US08435837B2

公开(公告)日：2013-05-07

申请号：US12638827

申请日：2009-12-15

申请人： Chen Lung Tsai ,  Long-Ching Wang ,  Tze-Pin Lin

发明人： Chen Lung Tsai ,  Long-Ching Wang ,  Tze-Pin Lin

IPC分类号： H01L21/00

CPC分类号： H01L23/5389 ,  H01L21/4832 ,  H01L21/568 ,  H01L23/495 ,  H01L23/49548 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A packaged semiconductor die has a preformed lead frame with a central recessed portion, and a plurality of conductive leads. An integrated circuit die has a top surface and a bottom surface opposite thereto, with the top surface having a plurality of bonding pads for electrical connection to the die. The die is positioned in the central recessed portion with the top surface having the bonding pads facing upward, and the bottom surface in contact with the recessed portion. Each of the leads has a top portion and a bottom portion. The leads are spaced apart and insulated from the central recessed portion. A conductive layer is deposited on the top surface of the die and the top portion of the leads and is patterned to electrically connect certain of the bonding pads of the die to certain of the conductive leads. An insulator covers the conductive layer. The present invention also relates to a method of packaging such an integrated circuit die.

摘要翻译： 封装的半导体管芯具有中心凹部的预成形引线框架和多个导电引线。 集成电路管芯具有与其相对的顶表面和底表面，其顶表面具有用于与管芯电连接的多个接合焊盘。 模具位于中央凹部中，顶表面具有面向上的接合焊盘，并且底表面与凹部接触。 每个引线具有顶部和底部。 引线间隔开并与中心凹部绝缘。 导电层沉积在管芯的顶表面和引线的顶部，并被图案化以将管芯的某些焊盘电连接到某些导电引线。 绝缘体覆盖导电层。 本发明还涉及一种封装这种集成电路管芯的方法。

公开(公告)号：US5045502A

公开(公告)日：1991-09-03

申请号：US522175

申请日：1990-05-10

申请人： Silvanius S. Lau ,  Timothy D. Sands ,  Long-Ching Wang

发明人： Silvanius S. Lau ,  Timothy D. Sands ,  Long-Ching Wang

IPC分类号： H01L21/285 ,  H01L29/45

CPC分类号： H01L21/28575 ,  H01L29/452 ,  H01L2224/05664 ,  H01L2224/45144 ,  H01L2224/48664 ,  H01L24/45 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/14

摘要： An ohmic contact to a semiconductor such as GaAs and its method of making in which a thin layer of Pd is overlaid preferably with a layer of Group-IV element such as Ge followed by another layer of Pd. This structure is then overlaid with a layer of Pd and In. The atomic ratio of the Pd and In in the entire structure lies between 0.9 and 1.5. This structure is then annealed at a temperature between 350.degree. C. and 675.degree. C. There results a very thin crystalline layer of Ge-doped InGaAs adjacent the GaAs and an overlying PdIn alloy layer providing a contact resistance in the range of 0.1-1 .OMEGA.-mm.

摘要翻译： 与诸如GaAs的半导体的欧姆接触及其制备方法，其中Pd的薄层优选地与诸如Ge之类的IV族元素层叠加，之后是另一层Pd。 然后用一层Pd和In覆盖该结构。 整个结构中Pd和In的原子比在0.9和1.5之间。 然后将该结构在350℃和675℃之间的温度下退火。结果，与GaAs相邻的Ge掺杂的InGaAs结晶层非常薄，并且覆盖在PdIn合金层上的接触电阻范围为0.1-1 欧米茄