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    Predictive Thermal Preconditioning and Timing Control for Non-Volatile Memory Cells
    1.
    发明申请
    Predictive Thermal Preconditioning and Timing Control for Non-Volatile Memory Cells 有权
    非易失性记忆体的预测热预处理和时序控制

    公开(公告)号：US20120147665A1

    公开(公告)日：2012-06-14

    申请号：US13400515

    申请日：2012-02-20

    申请人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  Dimitar V. Dimitrov ,  Alan Xuguang Wang ,  Xiaobin Wang

    发明人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  Dimitar V. Dimitrov ,  Alan Xuguang Wang ,  Xiaobin Wang

    IPC分类号： G11C11/16 ,  G11C7/00

    CPC分类号： G11C11/1675 ,  G11C11/1659

    摘要： Method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell. In accordance with some embodiments, a semiconductor memory has an array of non-volatile memory cells, and a control circuit which stores a first write command from a host to write data to said array. A write circuit flows a write current through an unconditioned first selected cell having a first block address associated with the first write command to write the first selected cell to a selected data state, and concurrently passes a thermal preconditioning current through a second selected cell having a second block address associated with the first block address. The write circuit further passes a thermal preconditioning current through a third selected cell having a third block address associated with the second block address in response to receipt by the control circuit of a second write command from the host associated with the second block address.

    摘要翻译： 使用热预处理将数据写入非易失性存储单元的方法和装置。 根据一些实施例，半导体存储器具有非易失性存储器单元的阵列，以及存储来自主机的第一写命令以将数据写入所述阵列的控制电路。 写入电路通过具有与第一写入命令相关联的第一块地址的无条件的第一选定单元流动写入电流，以将第一选定单元写入所选择的数据状态，并且同时通过热预处理电流通过具有 与第一块地址相关联的第二块地址。 响应于控制电路接收到与第二块地址相关联的主机的第二写入命令，写入电路进一步传递热预处理电流通过具有与第二块地址相关联的第三块地址的第三选定单元。

    FAULT-TOLERANT NON-VOLATILE BUDDY MEMORY STRUCTURE
    6.
    发明申请
    FAULT-TOLERANT NON-VOLATILE BUDDY MEMORY STRUCTURE 审中-公开
    故障的非易失性存储结构

    公开(公告)号：US20100037102A1

    公开(公告)日：2010-02-11

    申请号：US12269535

    申请日：2008-11-12

    申请人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  Alan Xuguang Wang ,  Song S. Xue

    发明人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  Alan Xuguang Wang ,  Song S. Xue

    IPC分类号： G06F11/16 ,  G06F11/00 ,  G06F12/08 ,  G06F12/00

    CPC分类号： G11C29/846

    摘要： Various embodiments of the present invention are generally directed to an apparatus and method for providing a fault-tolerant non-volatile buddy memory structure, such as a buddy cache structure for a controller in a data storage device. A semiconductor memory array of blocks of non-volatile resistive sense memory (RSM) cells is arranged to form a buddy memory structure comprising a first set of blocks in a first location of the array and a second set of blocks in a second location of the array configured to redundantly mirror the first set of blocks. A read circuit decodes a fault map which identifies a defect in a selected one of the first and second sets of blocks and concurrently outputs data stored in the remaining one of the first and second sets of blocks responsive to a data read operation upon said buddy memory structure.

    摘要翻译： 本发明的各种实施例通常涉及用于提供容错非易失性伙伴存储器结构的装置和方法，例如用于数据存储设备中的控制器的伙伴高速缓存结构。 布置非易失性电阻式感测存储器（RSM）单元块的半导体存储器阵列以形成伙伴存储器结构，其包括阵列的第一位置中的第一组块和位于阵列的第二位置的第二组块 阵列被配置为冗余地镜像第一组块。 读取电路解码故障映射，其识别所述第一和第二组块中的所选择的一个中的缺陷，并响应于所述好友存储器上的数据读取操作，同时输出存储在第一组和第二组中的剩余块中的数据 结构体。

    Memory hierarchy with non-volatile filter and victim caches
    7.
    发明授权
    Memory hierarchy with non-volatile filter and victim caches 有权
    具有非易失性过滤器和受害者缓存的内存层次结构

    公开(公告)号：US08966181B2

    公开(公告)日：2015-02-24

    申请号：US12332669

    申请日：2008-12-11

    申请人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  Alan Xuguang Wang

    发明人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  Alan Xuguang Wang

    IPC分类号： G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/0897 ,  G06F12/0811 ,  G06F2212/2024 ,  G06F2212/222 ,  Y02D10/13

    摘要： Various embodiments of the present invention are generally directed to an apparatus and method for non-volatile caching of data in a memory hierarchy of a data storage device. In accordance with some embodiments, a pipeline memory structure is provided to store data for use by a controller. The pipeline has a plurality of hierarchical cache levels each with an associated non-volatile filter cache and a non-volatile victim cache. Data retrieved from each cache level are respectively promoted to the associated non-volatile filter cache. Data replaced in each cache level are respectively demoted to the associated non-volatile victim cache.

    摘要翻译： 本发明的各种实施例一般涉及用于数据存储设备的存储器层级中的数据的非易失性缓存的装置和方法。 根据一些实施例，提供流水线存储器结构以存储要由控制器使用的数据。 流水线具有多个层次化的高速缓存级别，每一级具有关联的非易失性过滤器高速缓存和非易失性的受害者高速缓存。 从每个缓存级别检索的数据分别被提升到相关联的非易失性过滤器高速缓存。 每个缓存级别中替换的数据分别降级到相关的非易失性缓存缓存。

    Predictive thermal preconditioning and timing control for non-volatile memory cells
    8.
    发明授权
    Predictive thermal preconditioning and timing control for non-volatile memory cells 有权
    非易失性存储单元的预测性热预处理和时序控制

    公开(公告)号：US08553454B2

    公开(公告)日：2013-10-08

    申请号：US13400515

    申请日：2012-02-20

    申请人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  Dimitar V. Dimitrov ,  Alan Xuguang Wang ,  Xiaobin Wang

    发明人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  Dimitar V. Dimitrov ,  Alan Xuguang Wang ,  Xiaobin Wang

    IPC分类号： G11C11/14 ,  G11C8/00 ,  G11C7/00

    CPC分类号： G11C11/1675 ,  G11C11/1659

    摘要： Method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell. In accordance with some embodiments, a semiconductor memory has an array of non-volatile memory cells, and a control circuit which stores a first write command from a host to write data to said array. A write circuit flows a write current through an unconditioned first selected cell having a first block address associated with the first write command to write the first selected cell to a selected data state, and concurrently passes a thermal preconditioning current through a second selected cell having a second block address associated with the first block address. The write circuit further passes a thermal preconditioning current through a third selected cell having a third block address associated with the second block address in response to receipt by the control circuit of a second write command from the host associated with the second block address.

    摘要翻译： 使用热预处理将数据写入非易失性存储单元的方法和装置。 根据一些实施例，半导体存储器具有非易失性存储器单元的阵列，以及存储来自主机的第一写命令以将数据写入所述阵列的控制电路。 写入电路通过具有与第一写入命令相关联的第一块地址的无条件的第一选定单元流动写入电流，以将第一选定单元写入所选择的数据状态，并且同时通过热预处理电流通过具有 与第一块地址相关联的第二块地址。 响应于控制电路接收到与第二块地址相关联的主机的第二写入命令，写入电路进一步传递热预处理电流通过具有与第二块地址相关联的第三块地址的第三选定单元。