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    Semiconductor structure including high voltage device
    5.
    发明授权
    Semiconductor structure including high voltage device 有权
    半导体结构包括高压器件

    公开(公告)号：US08410553B2

    公开(公告)日：2013-04-02

    申请号：US12964753

    申请日：2010-12-10

    申请人： Jeoung Mo Koo ,  Purakh Raj Verma ,  Sanford Chu ,  Chunlin Zhu ,  Yisuo Li

    发明人： Jeoung Mo Koo ,  Purakh Raj Verma ,  Sanford Chu ,  Chunlin Zhu ,  Yisuo Li

    IPC分类号： H01L29/78

    CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/66568 ,  H01L29/7833

    摘要： A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure.

    摘要翻译： 高压器件包括其上限定有器件区域的衬底。 栅极堆叠设置在器件区域中的衬底上。 沟道区域位于栅堆叠下方的衬底中，而第一扩散区位于栅层叠的第一侧上的衬底中。 位于栅极堆叠的第一侧的衬底中的第一隔离结构分离通道和第一扩散区域。 高电压装置还包括在衬底中的第一漂移区域，其将沟道耦合到第一扩散区域，其中第一漂移区域包括符合第一隔离结构的轮廓的不均匀的深度分布。

    Semiconductor structure including high voltage device
    6.
    发明授权
    Semiconductor structure including high voltage device 有权
    半导体结构包括高压器件

    公开(公告)号：US07867862B2

    公开(公告)日：2011-01-11

    申请号：US11855168

    申请日：2007-09-14

    申请人： Jeoung Mo Koo ,  Purakh Raj Verma ,  Sanford Chu ,  Chunlin Zhu ,  Yisuo Li

    发明人： Jeoung Mo Koo ,  Purakh Raj Verma ,  Sanford Chu ,  Chunlin Zhu ,  Yisuo Li

    IPC分类号： H01L21/335

    CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/66568 ,  H01L29/7833

    摘要： A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure.

    摘要翻译： 高压器件包括其上限定有器件区域的衬底。 栅极堆叠设置在器件区域中的衬底上。 沟道区域位于栅堆叠下方的衬底中，而第一扩散区位于栅层叠的第一侧上的衬底中。 位于栅极堆叠的第一侧的衬底中的第一隔离结构分离通道和第一扩散区域。 高电压装置还包括在衬底中的第一漂移区域，其将沟道耦合到第一扩散区域，其中第一漂移区域包括符合第一隔离结构的轮廓的不均匀的深度分布。

    LDMOS using a combination of enhanced dielectric stress layer and dummy gates
    7.
    发明授权
    LDMOS using a combination of enhanced dielectric stress layer and dummy gates 有权
    LDMOS使用增强介电应力层和虚拟门的组合

    公开(公告)号：US08334567B2

    公开(公告)日：2012-12-18

    申请号：US12916653

    申请日：2010-11-01

    申请人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

    发明人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7835 ,  H01L29/404 ,  H01L29/456 ,  H01L29/49 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7843 ,  H01L29/7846

    摘要： First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprise forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region.

    摘要翻译： 第一示例实施例包括在由沟道和第一，第二和第三结区域构成的MOS晶体管（例如LDMOS Tx）上形成应力层。 应力层在通道和Tx的第二结区产生应力。 第二示例性实施例包括在衬底上形成MOS FET和至少一个虚拟栅极。 MOS由栅极，沟道，源极，漏极和漏极漏极组成。 至少一个虚拟栅极位于偏置漏极之上。 在MOS和虚拟栅极上形成应力层。 应力层和虚拟栅极改善了通道和偏移漏极区域的应力。

    LDMOS using a combination of enhanced dielectric stress layer and dummy gates
    8.
    发明授权
    LDMOS using a combination of enhanced dielectric stress layer and dummy gates 有权
    LDMOS使用增强介电应力层和虚拟门的组合

    公开(公告)号：US07824968B2

    公开(公告)日：2010-11-02

    申请号：US11488117

    申请日：2006-07-17

    申请人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

    发明人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

    IPC分类号： H01L21/332 ,  H01L21/336

    CPC分类号： H01L29/7835 ,  H01L29/404 ,  H01L29/456 ,  H01L29/49 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7843 ,  H01L29/7846

    摘要： First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprises forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region.

    摘要翻译： 第一示例实施例包括在由沟道和第一，第二和第三结区域构成的MOS晶体管（例如LDMOS Tx）上形成应力层。 应力层在通道和Tx的第二结区产生应力。 第二示例性实施例包括在衬底上形成MOS FET和至少一个虚拟栅极。 MOS由栅极，沟道，源极，漏极和漏极漏极组成。 至少一个虚拟栅极位于偏置漏极之上。 在MOS和虚拟栅极上形成应力层。 应力层和虚拟栅极改善了通道和偏移漏极区域的应力。

    LDMOS using a combination of enhanced dielectric stress layer and dummy gates
    9.
    发明申请
    LDMOS using a combination of enhanced dielectric stress layer and dummy gates 有权
    LDMOS使用增强介电应力层和虚拟门的组合

    公开(公告)号：US20080014690A1

    公开(公告)日：2008-01-17

    申请号：US11488117

    申请日：2006-07-17

    申请人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

    发明人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/7835 ,  H01L29/404 ,  H01L29/456 ,  H01L29/49 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7843 ,  H01L29/7846

    摘要： First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprises forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region

    摘要翻译： 第一示例实施例包括在由沟道和第一，第二和第三结区域构成的MOS晶体管（例如LDMOS Tx）上形成应力层。 应力层在通道和Tx的第二结区产生应力。 第二示例性实施例包括在衬底上形成MOS FET和至少一个虚拟栅极。 MOS由栅极，沟道，源极，漏极和漏极漏极组成。 至少一个虚拟栅极位于偏置漏极之上。 在MOS和虚拟栅极上形成应力层。 应力层和虚拟栅极改善了通道和偏移漏极区域的应力

    Structure and method to form source and drain regions over doped depletion regions
    10.
    发明授权
    Structure and method to form source and drain regions over doped depletion regions 有权
    在掺杂耗尽区上形成源极和漏极区的结构和方法

    公开(公告)号：US07888752B2

    公开(公告)日：2011-02-15

    申请号：US11706891

    申请日：2007-02-14

    申请人： King Jien Chui ,  Francis Benistant ,  Ganesh Shamkar Samudra ,  Kian Meng Tee ,  Yisuo Li ,  Kum Woh Vincent Leong ,  Kheng Chok Tee

    发明人： King Jien Chui ,  Francis Benistant ,  Ganesh Shamkar Samudra ,  Kian Meng Tee ,  Yisuo Li ,  Kum Woh Vincent Leong ,  Kheng Chok Tee

    IPC分类号： H01L29/78

    CPC分类号： H01L29/0847 ,  H01L21/823878 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/961

    摘要： A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.

    摘要翻译： 减小晶体管中源/漏区的结电容的结构和方法。 栅极结构形成在第一导电类型的衬底上。 我们通过使用栅极结构作为掩模将作为第二导电类型的离子注入到衬底来进行掺杂耗尽区域注入，以在源极/漏极区域之下形成掺杂的耗尽区域并从源极/漏极区域分离。 掺杂耗尽区具有杂质浓度和厚度，使得掺杂的耗尽区由于在掺杂的耗尽区和衬底之间可建立的内置势而耗尽。 掺杂耗尽区和衬底在源/漏区和掺杂耗尽区之间形成耗尽区。 我们通过将具有第二导电类型的离子注入到衬底中来形成S / D区域来进行S / D植入。 掺杂的耗尽区域和耗尽区域减小了源/漏区域和衬底之间的电容。