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    Double polysilicon bipolar transistor and method of manufacture therefor
    5.
    发明授权
    Double polysilicon bipolar transistor and method of manufacture therefor 有权
    双晶硅双极晶体管及其制造方法

    公开(公告)号：US06936519B2

    公开(公告)日：2005-08-30

    申请号：US10224111

    申请日：2002-08-19

    申请人： Purakh Raj Verma ,  Shao-fu Sanford Chu

    发明人： Purakh Raj Verma ,  Shao-fu Sanford Chu

    IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/732 ,  H01L29/737 ,  H01L21/8222

    CPC分类号： H01L29/66287 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/732 ,  H01L29/7375

    摘要： A bipolar transistor, and manufacturing method therefor, with a substrate having a collector region and a base structure provided thereon. An emitter structure is formed over the base structure and an extrinsic base structure is formed over the base structure and over the collector region beside and spaced from the emitter structure. A dielectric layer is deposited over the substrate and connections are formed to the extrinsic base structure, the emitter structure and the collector region.

    摘要翻译： 一种双极型晶体管及其制造方法，其上具有集电极区域和基极结构的基板。 在基底结构上形成发射极结构，并且在基极结构之上形成外部基极结构，并且在发射极结构旁边和间隔开的集电极区上方形成发射极结构。 电介质层沉积在衬底上，并且连接被形成为非本征基极结构，发射极结构和集电极区。

    INTEGRATED CIRCUIT SYSTEM WITH HIGH VOLTAGE TRANSISTOR AND METHOD OF MANUFACTURE THEREOF
    6.
    发明申请
    INTEGRATED CIRCUIT SYSTEM WITH HIGH VOLTAGE TRANSISTOR AND METHOD OF MANUFACTURE THEREOF 有权
    具有高压晶体管的集成电路系统及其制造方法

    公开(公告)号：US20100320529A1

    公开(公告)日：2010-12-23

    申请号：US12488451

    申请日：2009-06-19

    申请人： Yemin Dong ,  Purakh Raj Verma ,  Xin Zou ,  Chao Cheng ,  Shao-fu Sanford Chu

    发明人： Yemin Dong ,  Purakh Raj Verma ,  Xin Zou ,  Chao Cheng ,  Shao-fu Sanford Chu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/1041 ,  H01L29/4238

    摘要： A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and applying an isolation edge implant, with the impurities of the first type at a third concentration greater than or equal to the second concentration, for suppressing the parasitic transistor.

    摘要翻译： 一种集成电路系统的制造方法，包括：提供具有活性区域的半导体衬底，以第一浓度注入第一类型的杂质; 在活性区周围形成隔离区; 通过在有源区域和隔离区域上施加注入第二种类型的杂质的第二种浓度的栅电极来形成寄生晶体管; 以及施加隔离边缘注入，其中第一类型的杂质具有大于或等于第二浓度的第三浓度，用于抑制寄生晶体管。

    Method for forming a thin-film, electrically blowable fuse with a reproducible blowing wattage
    8.
    发明授权
    Method for forming a thin-film, electrically blowable fuse with a reproducible blowing wattage 有权
    用可重现的吹制瓦数形成薄膜可电熔熔断器的方法

    公开(公告)号：US06372652B1

    公开(公告)日：2002-04-16

    申请号：US09494633

    申请日：2000-01-31

    申请人： Purakh Raj Verma ,  Zia Alan Shafi ,  Yu Shan ,  Zeng Zheng ,  Manju Sarkar ,  Shao-Fu Sanford Chu

    发明人： Purakh Raj Verma ,  Zia Alan Shafi ,  Yu Shan ,  Zeng Zheng ,  Manju Sarkar ,  Shao-Fu Sanford Chu

    IPC分类号： H01L21302

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a thin film, electrically blowable fuse with reproducible blowing wattage using a sacrificial metal patch over a fuse dielectric layer and two etch processes; wherein the first etch process is selective to the metal patch and the second etch process is selective to the fuse dielectric layer. A fuse element, having an element width, is formed over a semiconductor structure, and a fuse dielectric layer is formed over the fuse element. A sacrificial metal patch is formed on the fuse dielectric layer; wherein the patch width being greater than the fuse element width. A second dielectric layer is formed on the sacrificial metal patch, and additional metal layers and dielectric layers may be formed over the second dielectric layer, but only the dielectric layers will remain over the fuse element. The second dielectric layer and any overlying dielectric layers are patterned to form a fuse window opening, having a width greater than the sacrificial metal patch, using a first fuse window etch selective to the sacrificial metal patch. Then, the sacrificial metal patch is etched through the fuse window opening using a second fuse window etch selective to the fuse dielectric layer, leaving a reproducible thickness of the fuse dielectric layer overlying the fuse element; thereby providing a reproducible blowing wattage.

    摘要翻译： 一种用于在熔丝电介质层和两个蚀刻工艺上使用牺牲金属贴片形成具有可再现的吹扫功率的薄膜电可熔电熔丝的方法; 其中所述第一蚀刻工艺对所述金属贴片是选择性的，并且所述第二蚀刻工艺对所述熔丝电介质层是选择性的。 在半导体结构上形成具有元件宽度的熔丝元件，并且在保险丝元件上形成熔丝电介质层。 在熔丝绝缘层上形成牺牲金属贴片; 其中所述贴片宽度大于所述熔丝元件宽度。 在牺牲金属贴片上形成第二电介质层，并且可以在第二电介质层上形成附加的金属层和电介质层，但是只有电介质层将保留在熔丝元件上方。 使用对牺牲金属贴片选择性的第一熔丝窗口蚀刻，将第二电介质层和任何上覆电介质层图案化以形成具有大于牺牲金属贴片的宽度的熔丝窗口。 然后，使用对熔丝电介质层选择性的第二熔丝窗蚀刻，通过熔丝窗口蚀刻牺牲金属贴片，留下覆于熔丝元件上的熔丝电介质层的可再现厚度; 从而提供可重复的吹制瓦数。

    Double polysilicon bipolar transistor
    9.
    发明授权
    Double polysilicon bipolar transistor 有权
    双晶硅双极晶体管

    公开(公告)号：US07268412B2

    公开(公告)日：2007-09-11

    申请号：US11057259

    申请日：2005-02-12

    申请人： Purakh Raj Verma ,  Shao-fu Sanford Chu

    发明人： Purakh Raj Verma ,  Shao-fu Sanford Chu

    IPC分类号： H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

    CPC分类号： H01L29/66287 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/732 ,  H01L29/7375

    摘要： A bipolar transistor with a substrate having a collector region and a base structure provided thereon. An emitter structure is formed over the base structure and an extrinsic base structure is formed over the base structure and over the collector region beside and spaced from the emitter structure. A dielectric layer is deposited over the substrate and connections are formed to the extrinsic base structure, the emitter structure and the collector region.

    摘要翻译： 一种双极晶体管，其具有设置在其上的集电极区域和基极结构的衬底。 在基底结构上形成发射极结构，并且在基极结构之上形成外部基极结构，并且在发射极结构旁边和间隔开的集电极区上方形成发射极结构。 电介质层沉积在衬底上，并且连接被形成为非本征基极结构，发射极结构和集电极区。

    Self-aligned lateral heterojunction bipolar transistor
    10.
    发明授权
    Self-aligned lateral heterojunction bipolar transistor 有权
    自对准横向异质结双极晶体管

    公开(公告)号：US07238971B2

    公开(公告)日：2007-07-03

    申请号：US11123748

    申请日：2005-05-04

    申请人： Jian Xun Li ,  Lap Chan ,  Purakh Raj Verma ,  Jia Zhen Zheng ,  Shao-fu Sanford Chu

    发明人： Jian Xun Li ,  Lap Chan ,  Purakh Raj Verma ,  Jia Zhen Zheng ,  Shao-fu Sanford Chu

    IPC分类号： H01L29/732

    CPC分类号： H01L29/66242 ,  H01L29/737

    摘要： A lateral heterojunction bipolar transistor (HBT) comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

    摘要翻译： 一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。 基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。 半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。 基底结构形成在基底沟槽中。 通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。 基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。