公开(公告)号：US20070291557A1

公开(公告)日：2007-12-20

申请号：US11761470

申请日：2007-06-12

申请人： Yoji NISHIO ,  Yutaka UEMATSU ,  Seiji FUNABA ,  Hideki OSAKA ,  Tsutomu HARA ,  Koichiro AOKI

发明人： Yoji NISHIO ,  Yutaka UEMATSU ,  Seiji FUNABA ,  Hideki OSAKA ,  Tsutomu HARA ,  Koichiro AOKI

IPC分类号： G11C5/06 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/02 ,  G11C5/02 ,  G11C5/04 ,  H01L25/105 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

摘要： Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.

摘要翻译： 堆叠的半导体器件包括堆叠在一起的多个存储器芯片，其中高速传输中的波形失真被去除。 堆叠半导体器件1包括堆叠在一起的多个存储器芯片11,12。 作为用于每周期两次输入/输出数据的控制信号的数据选通信号（DQS）和反相数据选通信号（/ DQS）被用作两个单端数据选通信号。 数据选通信号和反相数据选通信号相互配合。 用于数据选通信号L 4的数据选通信号线连接到第一存储芯片11的数据选通信号（DQS）焊盘。用于DQS信号L 5的反相数据选通信号线连接到反相数据选通信号（/ DQS）焊盘 的第二存储器芯片12。

公开(公告)号：US20080203554A1

公开(公告)日：2008-08-28

申请号：US12113414

申请日：2008-05-01

申请人： Yoji NISHIO ,  Seiji FUNABA

发明人： Yoji NISHIO ,  Seiji FUNABA

IPC分类号： H01L23/02 ,  H01L23/12

CPC分类号： H01L23/66 ,  G06F1/184 ,  G06F1/185 ,  G06F1/186 ,  G11C5/025 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/50 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01068 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K1/141 ,  H01L2924/00

摘要： A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.

摘要翻译： 包括多个堆叠的DRAM芯片的COC DRAM通过使用插入件安装在母板上。 插入器包括Si单元和PCB。 Si单元包括Si基板和布置布线的绝缘层单元。 PCB包括用于Si单元中布线的参考平面。 芯片组和COC DRAM之间的布线结构对于每个信号是相同的。 因此，提供了能够进行高速运转，低功耗，大容量的存储器系统。

公开(公告)号：US20120051099A1

公开(公告)日：2012-03-01

申请号：US13213239

申请日：2011-08-19

申请人： Seiji FUNABA ,  Yasuo Noto ,  Masashige Tsuji

发明人： Seiji FUNABA ,  Yasuo Noto ,  Masashige Tsuji

IPC分类号： H02M3/335

CPC分类号： H02M1/08 ,  H02M3/335 ,  H02M7/5387 ,  H02M2001/0006 ,  H02M2001/0025 ,  H03K17/04123

摘要： A power conversion device includes an inverter circuit converting DC power into AC power and including switching devices constituting upper and lower arms, a control circuit controlling the switching devices, a drive circuit driving the switching devices by a signal from the control circuit, and an insulated power supply circuit supplying power to the drive circuit. The control circuit controls a power supply voltage to be outputted from the power supply circuit to the drive circuit. The drive circuit drives the switching devices and based on a carrier frequency and the power supply voltage. The power supply circuit includes a feedback output circuit through which the voltage outputted to the drive circuit is outputted to a power supply control IC. The feedback output circuit includes a dummy load circuit which controls the voltage to be outputted to the power supply control IC based on a change of the carrier frequency.

摘要翻译： 电力转换装置包括将直流电变换为交流电的逆变器电路，包括构成上臂和下臂的开关装置，控制开关装置的控制电路，通过来自控制电路的信号驱动开关装置的驱动电路，以及绝缘 电源电路向驱动电路供电。 控制电路控制从电源电路向驱动电路输出的电源电压。 驱动电路驱动开关器件，并根据载波频率和电源电压。 电源电路包括输出到驱动电路的电压输出到电源控制IC的反馈输出电路。 反馈输出电路包括基于载波频率的变化来控制输出到电源控制IC的电压的虚拟负载电路。