公开(公告)号：US5910675A

公开(公告)日：1999-06-08

申请号：US763513

申请日：1996-12-11

申请人： Yoko Horiguchi ,  Kaoru Narita ,  Takeo Fujii

发明人： Yoko Horiguchi ,  Kaoru Narita ,  Takeo Fujii

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L29/72

CPC分类号： H01L27/0248 ,  H01L27/0635

摘要： A semiconductor device includes a metal terminal provided on a semiconductor substrate and a protection element. The protection element includes an insulated gate field-effect transistor. The transistor has a first diffusion layer of a reverse conductive-type formed on one conductive type region of the semiconductor substrate and connected to the metal terminal, as its source. The transistor also includes a second diffusion layer of a reverse conductive-type connected to an electrode wire having a constant electric potential, as its source, and has a gate electrode connected to the electrode wire. A lateral bipolar transistor includes a third diffusion layer of a reverse conductive-type formed with a constant spaced distance with respect to the second diffusion layer and connected to the metal terminal, as its collector, and also has the second diffusion layer as its emitter, and furthermore has the one conductive-type region as its base. Thus, a semiconductor device is protected from an electrostatic discharge (ESD) breakdown device even though having high density and a high operating speed.

摘要翻译： 半导体器件包括设置在半导体衬底上的金属端子和保护元件。 保护元件包括绝缘栅场效应晶体管。 晶体管具有形成在半导体衬底的一个导电类型区域上并以金属端子连接的反向导电型的第一扩散层作为其源极。 晶体管还包括连接到具有恒定电位的电极线作为其源极的反向导电型的第二扩散层，并且具有连接到电极线的栅电极。 横向双极晶体管包括反向导电型的第三扩散层，该第三扩散层相对于第二扩散层具有恒定的间隔距离并且连接到作为其集电极的金属端子，并且还具有第二扩散层作为其发射极， 并且还具有一个导电型区域作为其基底。 因此，即使具有高密度和高操作速度，半导体器件也被保护免受静电放电（ESD）击穿器件的影响。

公开(公告)号：US5449939A

公开(公告)日：1995-09-12

申请号：US364275

申请日：1994-12-27

申请人： Yoko Horiguchi ,  Kaoru Narita

发明人： Yoko Horiguchi ,  Kaoru Narita

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L27/0259

摘要： A semiconductor device has an internal circuit, an output transistor and a protective transistor for protecting the output transistor and the internal circuit against an ESD-induced destruction caused by a surge pulse entering from an input/output terminal. The sum of a first distance between a contact for connecting an input/output terminal with the collector of the protective transistor and a field oxide film and a second distance between a contact for connecting the input/output terminal with the emitter of the protective transistor and the field oxide film overlying the base of the laterally formed protective transistor is made smaller than the sum of a third distance between a contact for connecting the input/output terminal with the drain of the output transistor and the gate electrode of the output transistor and a fourth distance between a contact for connecting a potential line with the source of the output transistor and the gate electrode of the output transistor. Besides, the effective channel length of the output transistor is made longer than the effective base width of the protective transistor.

摘要翻译： 半导体器件具有内部电路，输出晶体管和保护晶体管，用于保护输出晶体管和内部电路免受由输入/输出端子进入的浪涌脉冲引起的ESD引起的破坏。 用于将输入/输出端子与保护晶体管的集电极连接的触头与场氧化膜之间的第一距离与用于将输入/输出端子与保护晶体管的发射极连接的触点之间的第二距离之和，以及 使横向形成的保护晶体管的基部覆盖的场氧化膜小于用于将输入/输出端子与输出晶体管的漏极和输出晶体管的栅极连接的触点之间的第三距离和 用于将电位线与输出晶体管的源极和输出晶体管的栅电极连接的触点之间的第四距离。 此外，输出晶体管的有效沟道长度比保护晶体管的有效基极宽度长。

公开(公告)号：US06175139B1

公开(公告)日：2001-01-16

申请号：US09192473

申请日：1998-11-17

申请人： Yoko Horiguchi ,  Kaoru Narita ,  Takeo Fujii

发明人： Yoko Horiguchi ,  Kaoru Narita ,  Takeo Fujii

IPC分类号： H01L2972

CPC分类号： H01L27/0248 ,  H01L27/0635

摘要： A semiconductor device includes a metal terminal provided on a semiconductor substrate and a protection element. The protection element includes an insulated gate field-effect transistor. The transistor has a first diffusion layer of a reverse conductive-type formed on one conductive type region of the semiconductor substrate and connected to the metal terminal, as its source. The transistor also includes a second diffusion layer of a reverse conductive-type connected to an electrode wire having a constant electric potential, as its source, and has a gate electrode connected to the electrode wire. A lateral bipolar transistor includes a third diffusion layer of a reverse conductive-type formed with a constant spaced distance with respect to the second diffusion layer and connected to the metal terminal, as its collector, and also has the second diffusion layer as its emitter, and furthermore has the one conductive-type region as its base. Thus, a semiconductor device is protected from an electrostatic discharge (ESD) breakdown device even though having high density and a high operating speed.

摘要翻译： 半导体器件包括设置在半导体衬底上的金属端子和保护元件。 保护元件包括绝缘栅场效应晶体管。 晶体管具有形成在半导体衬底的一个导电类型区域上并以金属端子连接的反向导电型的第一扩散层作为其源极。 晶体管还包括连接到具有恒定电位的电极线作为其源极的反向导电型的第二扩散层，并且具有连接到电极线的栅电极。 横向双极晶体管包括反向导电型的第三扩散层，该第三扩散层相对于第二扩散层具有恒定的间隔距离并且连接到作为其集电极的金属端子，并且还具有第二扩散层作为其发射极， 并且还具有一个导电型区域作为其基底。 因此，即使具有高密度和高操作速度，半导体器件也被保护免受静电放电（ESD）击穿器件的影响。

公开(公告)号：US6101078A

公开(公告)日：2000-08-08

申请号：US149112

申请日：1998-09-09

申请人： Takeo Fujii ,  Kaoru Narita ,  Yoko Horiguchi

发明人： Takeo Fujii ,  Kaoru Narita ,  Yoko Horiguchi

IPC分类号： H01L23/495 ,  H01L23/60 ,  H01L27/02 ,  H02H9/04 ,  H02H3/00

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/60 ,  H01L27/0248 ,  H02H9/046 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107

摘要： A lead on chip (LOC) semiconductor device or a chip on lead (COL) semiconductor device with a protection circuit. Non-connection pins are made shorter than connection pins to reduce the inductance of the non-connection pins, or to obtain a different capability of the protection circuit for non-connection pins with respect to connection pins. The time constant of the protection circuit for the non-connection pins is made longer than that of the protection circuit for the connection pins. Further, the clamping capability for the connection pins is made greater than that for another connection pin adjacent to the connection pin.

摘要翻译： 具有保护电路的片上芯片（LOC）半导体器件或引线（COL）半导体器件芯片。 非连接引脚比连接引脚短，以减少非连接引脚的电感，或者获得与连接引脚相关的非连接引脚的保护电路的不同能力。 非连接引脚的保护电路的时间常数比连接引脚的保护电路的时间常数长。 此外，连接销的夹紧能力大于与连接销相邻的另一个连接销的夹紧能力。

公开(公告)号：US06191633B1

公开(公告)日：2001-02-20

申请号：US09149115

申请日：1998-09-09

申请人： Takeo Fujii ,  Kaoru Narita ,  Yoko Horiguchi

发明人： Takeo Fujii ,  Kaoru Narita ,  Yoko Horiguchi

IPC分类号： H03K508

CPC分类号： H03K5/08 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0288 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Semiconductor integrated circuit with a protection circuit against electrostatic discharge. A clamping element is connected with MIS transistor to prevent the breakdown under the charged device model. A parasitic bipolar transistor, a MOS transistor or MIS transistor whose gate is composed of an insulating film thicker than that of the transfer gate, can be used as the clamping element.

摘要翻译： 一个具有防静电放电保护电路的半导体集成电路。 夹紧元件与MIS晶体管连接，以防止充电器件型号下的击穿。 可以使用寄生双极晶体管，MOS晶体管或MIS晶体管，其栅极由比传输栅极厚的绝缘膜构成，可用作夹紧元件。

公开(公告)号：US06414341B1

公开(公告)日：2002-07-02

申请号：US09401129

申请日：1999-09-22

申请人： Yoko Horiguchi

发明人： Yoko Horiguchi

IPC分类号： H01L2710

CPC分类号： H01L23/62 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an excellent input/output protective device which has a withstand voltage of 200 V or more in device simulation tests according to the EOS/ESD standard. There is presented an input/output device having a protective element that prevents external noise from degrading the internal circuit therein by inducing an electric discharge between diffusion layers of the second conductive type thereof which are disposed on a semiconductor substrate of the first conductive type and facing each other; wherein there are equipped with a plurality of contacts each of which connects a metal wiring layer with a diffusion layer; and a contact at the end section of the protective element on the side of the input section, at least, is provided with a means to increase the resistance thereof so as to make that larger than the resistance of the other contacts.

摘要翻译： 本发明提供了在根据EOS / ESD标准的器件模拟测试中具有200V或更高的耐受电压的优异的输入/输出保护器件。 提出了一种具有保护元件的输入/输出装置，其防止外部噪声通过在第二导电类型的第二导电类型的扩散层之间引起放电而防止其内部电路降解，该第二导电类型的扩散层设置在第一导电类型的半导体基板上并面向 彼此; 其中配备有多个触点，每个触点将金属布线层与扩散层连接; 并且至少在输入部分一侧的保护元件的端部处的触点设置有增加其电阻以使其大于其它触点的电阻的装置。

公开(公告)号：US06943412B1

公开(公告)日：2005-09-13

申请号：US09615705

申请日：2000-07-13

申请人： Yoko Horiguchi

发明人： Yoko Horiguchi

IPC分类号： H01L21/822 ,  H01L21/8234 ,  H01L23/62 ,  H01L27/04 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L27/0647 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/0676 ,  H01L27/0811 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit is provided, which has an improved withstanding voltage for electrostatic breakdown at the time of electrostatic discharge by the charged device model, in the case of protecting a MOS capacitor provided at the input side of the internal circuit. The semiconductor integrated circuit comprises an internal circuit 20 for inputting an external signal, an internal circuit MOS capacitor 16, one end of which is connected to a power source wire 10 for supplying the source voltage and the other end of which is connected to a ground potential wire 12 for supplying the ground potential; a ground terminal 14 to which one end of the ground potential wire is connected; an electrostatic protection element 18 connected in parallel with the MOS capacitor 16 between the ground terminal 14 and the MOS capacitor, wherein the MOS capacitor and the electrostatic protection element are connected between the power source wire and the ground potential wire such that the wire resistance R1 of the ground potential wire between the ground terminal and the connection point with one end of the electrostatic protection element is larger than the wire resistance R2 of the ground potential wire between the connection point with one end of the electrostatic protection element and the connection point with one end of the MOS capacitor.

摘要翻译： 在保护设置在内部电路的输入侧的MOS电容器的情况下，提供了一种半导体集成电路，其具有用于通过充电装置型号的静电放电时的静电击穿的耐受电压。 半导体集成电路包括用于输入外部信号的内部电路20，内部电路MOS电容器16，其一端连接到用于提供源极电压并且另一端连接到地的电源线10 用于提供地电位的电位线12; 地电位线的一端连接到的接地端子14; 在接地端子14和MOS电容器之间与MOS电容器16并联连接的静电保护元件18，其中MOS电容器和静电保护元件连接在电源线和接地电位线之间，使得线电阻R 接地端子与静电保护元件一端的连接点之间的接地电位线1之间的距离大于静电保护元件一端的连接点与连接点之间的地电位线的线电阻R 2 点与MOS电容器的一端。

公开(公告)号：US5932914A

公开(公告)日：1999-08-03

申请号：US898344

申请日：1997-07-22

申请人： Yoko Horiguchi

发明人： Yoko Horiguchi

IPC分类号： H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088

CPC分类号： H01L27/0248

摘要： The present invention provides an electrostatic breakdown protecting device which has a high electrostatic breakdown resistance, a high latch up resistance and an excellent protective ability and which has no dead space in the vicinity of protective elements. The present invention includes an I/O terminal directly connected to a protective diode comprising a p-type diffusion layer 103a and an n-type diffusion layer 102b, and an NPN protective bipolar transistor comprising n-type diffusion layers 102b, 102c and a p-type well 113 and connected to an NMOSFET for protection comprising n-type diffusion layers 102c, 102d and a gate electrode 105 via an input resistor 114. These protective elements are formed on the p-type well 113 separated from a substrate for an internal circuit by an n-type buried diffusion layer 111 and an n-type well 112. The internal circuit to be protected is connected to a drain 102d of the NMOSFET for protection.

摘要翻译： 本发明提供一种具有高静电击穿电阻，高闩锁电阻和优异的保护能力并且在保护元件附近没有死角的静电击穿保护装置。 本发明包括直接连接到包括p型扩散层103a和n型扩散层102b的保护二极管的I / O端子，以及包括n型扩散层102b，102c和p的NPN保护双极晶体管 型阱113并且经由输入电阻器114连接到用于保护的NMOSFET，其包括n型扩散层102c，102d和栅电极105.这些保护元件形成在与用于内部的衬底的衬底分离的p型阱113上 电路由n型掩埋扩散层111和n型阱112.被保护的内部电路连接到NMOSFET的漏极102d以进行保护。