公开(公告)号：US20060255449A1

公开(公告)日：2006-11-16

申请号：US11354177

申请日：2006-02-15

申请人： Yonggill Lee ,  Kyungsoo Rho ,  Taejun Jeong

发明人： Yonggill Lee ,  Kyungsoo Rho ,  Taejun Jeong

IPC分类号： H01L23/04 ,  H01L23/52 ,  H01L23/24 ,  H01L23/02 ,  H01L23/495

CPC分类号： H01L25/105 ,  H01L23/04 ,  H01L23/10 ,  H01L24/48 ,  H01L25/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to a lid and a package structure having the same. The package structure comprises a first substrate, a first chip, a lid and a second package. The first chip is disposed on and electrically connected to the top surface of the first substrate. The lid is disposed on the top surface of the first substrate and comprises a body, a plurality of through holes and a cavity. The through holes penetrate the body and have a conductive material therein. The cavity accommodates the first chip. The second package is on the lid and is electrically connected to the first substrate through the conductive material in the through holes. As a result, the amount of the signal path between the second package and the first substrate is increased, and the manufacturing cost of the package structure is low.

摘要翻译： 本发明涉及一种盖子及具有该盖子的包装结构。 封装结构包括第一衬底，第一芯片，盖子和第二封装。 第一芯片设置在电连接到第一基板的顶表面上。 盖设置在第一基板的顶表面上，并且包括主体，多个通孔和空腔。 通孔穿透主体并在其中具有导电材料。 空腔容纳第一芯片。 第二包装在盖上，并且通过通孔中的导电材料电连接到第一基板。 结果，第二封装和第一基板之间的信号路径的量增加，并且封装结构的制造成本低。

公开(公告)号：US20070020802A1

公开(公告)日：2007-01-25

申请号：US11357952

申请日：2006-02-22

申请人： Yonggill Lee ,  Kwangwon Koh ,  Sangyun Lee

发明人： Yonggill Lee ,  Kwangwon Koh ,  Sangyun Lee

IPC分类号： H01L21/00

CPC分类号： H01L23/49575 ,  H01L23/49503 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： The present invention relates to a packaging method for segregating die paddles of a leadframe. The method comprising: (a) providing a leadframe having a top surface, a bottom surface and a die paddle region, the die paddle region having a plurality of die paddles, wherein at least two of the die paddles are connected to each other by at least one connecting bar; (b) attaching a plurality of dies onto the die paddles; (c) forming a molding compound to encapsulating the dies on the die paddles, and exposing the bottom surface of the connecting bar outside the molding compound; and (d) removing part of the connecting bar so as to segregate the die paddles, Whereby the die paddles are stable during the steps of die attaching, wire bonding and molding, and the yield is raised.

摘要翻译： 本发明涉及一种用于隔离引线框的芯片的封装方法。 该方法包括：（a）提供具有顶表面，底表面和管芯焊盘区域的引线框架，所述管芯焊盘区域具有多个管芯焊盘，其中至少两个管芯焊盘彼此连接在一起 至少一个连接条; （b）将多个模具附接到模片上; （c）形成模塑料以将模具封装在模片上，并将连接条的底表面暴露在模塑料外部; 并且（d）去除连接杆的一部分以使模片分离，由此在模具附接，线接合和模制的步骤期间，模片稳定，并且产量提高。

公开(公告)号：US07456053B2

公开(公告)日：2008-11-25

申请号：US11357952

申请日：2006-02-22

申请人： Yonggill Lee ,  Kwangwon Koh ,  Sangyun Lee

发明人： Yonggill Lee ,  Kwangwon Koh ,  Sangyun Lee

IPC分类号： H01L21/48

CPC分类号： H01L23/49575 ,  H01L23/49503 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A packaging method for segregating die paddles of a leadframe, includes (a) providing a leadframe having a top surface, a bottom surface and a die paddle region, the die paddle region having a plurality of die paddles, wherein at least two of the die paddles are connected to each other by at least one connecting bar; (b) attaching a plurality of dies onto the die paddles; (c) forming a molding compound to encapsulate the dies on the die paddles, and exposing the bottom surface of the connecting bar outside the molding compound; and (d) removing part of the connecting bar so as to segregate the die paddles. The die paddles are thus rendered stable during the steps of die attaching, wire bonding and molding, and the yield is raised.

摘要翻译： 用于分离引线框的芯片的封装方法包括（a）提供具有顶表面，底表面和管芯焊盘区域的引线框架，所述管芯焊盘区域具有多个管芯焊盘，其中至少两个管芯 桨叶通过至少一个连接杆彼此连接; （b）将多个模具附接到模片上; （c）形成模塑料以将模具封装在模片上，并将连接杆的底表面暴露于模塑料外部; 和（d）去除连接杆的一部分以使模片分离。 因此，在管芯附着，引线接合，成型的工序中，芯片桨稳定，成品率提高。

公开(公告)号：US07408244B2

公开(公告)日：2008-08-05

申请号：US11416206

申请日：2006-05-03

申请人： Yonggill Lee ,  Sangbae Park

发明人： Yonggill Lee ,  Sangbae Park

IPC分类号： H01L23/495

CPC分类号： H01L23/49551 ,  H01L23/3107 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor package includes a semiconductor chip electrically connected to a plurality of leads arranged at the periphery of the semiconductor chip wherein each of the leads is bent to have a first portion exposed from the upper surface of the semiconductor package and a second portion exposed from the lower surface of the semiconductor package. Both of the first portion and the second portion of each lead can be utilized for making external electrical connection.

摘要翻译： 半导体封装包括电连接到布置在半导体芯片的周边的多个引线的半导体芯片，其中每个引线被弯曲以具有从半导体封装的上表面露出的第一部分和从该半导体封装的上表面露出的第二部分 半导体封装的下表面。 每个引线的第一部分和第二部分都可用于进行外部电连接。

公开(公告)号：US20060261453A1

公开(公告)日：2006-11-23

申请号：US11416206

申请日：2006-05-03

申请人： Yonggill Lee ,  Sangbae Park

发明人： Yonggill Lee ,  Sangbae Park

IPC分类号： H01L23/495

CPC分类号： H01L23/49551 ,  H01L23/3107 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor package includes a semiconductor chip electrically connected to a plurality of leads arranged at the periphery of the semiconductor chip wherein each of the leads is bent to have a first portion exposed from the upper surface of the semiconductor package and a second portion exposed from the lower surface of the semiconductor package. Both of the first portion and the second portion of each lead can be utilized for making external electrical connection.

摘要翻译： 半导体封装包括电连接到布置在半导体芯片的周边的多个引线的半导体芯片，其中每个引线被弯曲以具有从半导体封装的上表面露出的第一部分和从该半导体封装的上表面露出的第二部分 半导体封装的下表面。 每个引线的第一部分和第二部分都可用于进行外部电连接。

公开(公告)号：US20070254406A1

公开(公告)日：2007-11-01

申请号：US11819624

申请日：2007-06-28

申请人： Yonggill Lee

发明人： Yonggill Lee

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A method for manufacturing a stacked package structure is disclosed, comprising: forming a first chip package structure, comprising: providing a chip carrier having a first and a second surface in opposition to each other; forming bonding wires on the first surface; providing at least one chip on and electrically connected to the first surface; and forming an encapsulant covering the first surface, the chip and the bonding wires, wherein a top end of each bonding wire is exposed at a surface of the encapsulant; forming a plurality of electrical connections respectively deposed on the top end of each bonding wire; and providing a second chip structure electrically jointed with the electrical connections and stacked on the first chip package structure.

摘要翻译： 公开了一种用于制造堆叠封装结构的方法，包括：形成第一芯片封装结构，包括：提供具有彼此相对的第一和第二表面的芯片载体; 在第一表面上形成接合线; 在所述第一表面上提供至少一个芯片并电连接到所述第一表面; 以及形成覆盖所述第一表面，所述芯片和所述接合线的密封剂，其中每个接合线的顶端在所述密封剂的表面处露出; 形成分别放置在每个接合线的顶端上的多个电连接; 以及提供与所述电连接电连接并堆叠在所述第一芯片封装结构上的第二芯片结构。

公开(公告)号：US07242081B1

公开(公告)日：2007-07-10

申请号：US11409933

申请日：2006-04-24

申请人： Yonggill Lee

发明人： Yonggill Lee

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A stacked package structure and a method for manufacturing the same are disclosed. The package structure comprises: a substrate having a first surface and a second surface in opposition to each other; at least one chip deposed on and electrically connected to the first surface of the substrate; a plurality of electrical connection devices deposed on the first surface and periphery of the substrate, wherein each electrical connection device is higher than the at least one chip in altitude; and an encapsulant covering the first surface of the substrate, the at least one chip and the electrical connection devices, wherein a top end of each electrical connection device is exposed at a surface of the encapsulant.

摘要翻译： 公开了堆叠式封装结构及其制造方法。 封装结构包括：具有彼此相对的第一表面和第二表面的基板; 至少一个芯片放置在基板的第一表面上并电连接到基板的第一表面; 多个电连接装置，其设置在所述基板的所述第一表面和周边上，其中每个电连接装置高于所述至少一个高度的芯片; 以及覆盖所述基板的所述第一表面，所述至少一个芯片和所述电连接装置的密封剂，其中每个电连接装置的顶端在所述密封剂的表面处露出。