公开(公告)号：USD290958S

公开(公告)日：1987-07-21

申请号：US670849

申请日：1984-11-13

申请人： Yoshiaki Kawata ,  Masaki Yamamoto ,  Toyoyuki Uematsu ,  Hiroyuki Tsubaki ,  Yutaka Itoh

设计人： Yoshiaki Kawata ,  Masaki Yamamoto ,  Toyoyuki Uematsu ,  Hiroyuki Tsubaki ,  Yutaka Itoh

公开(公告)号：USD282170S

公开(公告)日：1986-01-14

申请号：US537238

申请日：1983-09-29

申请人： Hiroyuki Tsubaki ,  Yoshiaki Kawata ,  Yutaka Itoh ,  Toyoyuki Uematsu

设计人： Hiroyuki Tsubaki ,  Yoshiaki Kawata ,  Yutaka Itoh ,  Toyoyuki Uematsu

公开(公告)号：USD290007S

公开(公告)日：1987-05-26

申请号：US649022

申请日：1984-09-10

申请人： Kazunori Mano ,  Yoshiaki Kawata ,  Yutaka Itoh

设计人： Kazunori Mano ,  Yoshiaki Kawata ,  Yutaka Itoh

公开(公告)号：US08070252B2

公开(公告)日：2011-12-06

申请号：US12035897

申请日：2008-02-22

申请人： Yutaka Itoh ,  Kazuya Tashiro

发明人： Yutaka Itoh ,  Kazuya Tashiro

IPC分类号： B41J29/393 ,  B41J29/38

CPC分类号： G03G15/161 ,  G03G15/55

摘要： An image forming apparatus includes a transport belt, a carriage, a reflection sensor, and a control unit. The transport belt transports a recording sheet in a sub-scanning direction. The carriage, mounting a recording head, reciprocally moves in a main scanning direction to record an image on the recording sheet. The reflection sensor, mounted on the carriage, receives light reflected from the transport belt to detect a leading edge of the recording sheet, and outputs a detection signal corresponding to the received light. The control unit controls a contamination check process. The control unit instructs the carriage to move to a given position over the transport belt and to drive the transport belt for one rotation while maintaining the carriage at the given position. The control unit determines whether contamination exists on the transport belt based on the detection signal output from the reflection sensor.

摘要翻译： 图像形成装置包括传送带，托架，反射传感器和控制单元。 传送带沿副扫描方向传送记录纸。 安装记录头的托架在主扫描方向上往复运动，以将图像记录在记录纸上。 安装在托架上的反射传感器接收从传送带反射的光以检测记录纸的前缘，并输出与接收到的光对应的检测信号。 控制单元控制污染检查过程。 控制单元指示滑架移动到传送带上方的给定位置，并将传送带驱动一圈，同时将滑架保持在给定位置。 控制单元基于从反射传感器输出的检测信号确定传送带上是否存在污染物。

公开(公告)号：US07888801B2

公开(公告)日：2011-02-15

申请号：US12430439

申请日：2009-04-27

申请人： Koji Takemura ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Masao Takahashi ,  Koji Koike

发明人： Koji Takemura ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Masao Takahashi ,  Koji Koike

IPC分类号： H01L23/522

CPC分类号： H01L23/585 ,  H01L21/76832 ,  H01L23/522 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.

摘要翻译： 一种半导体器件包括在半导体衬底上的层间绝缘膜中堆叠的至少三个或更多个布线层，设置在半导体衬底的芯片区域的外周处的密封环和在芯片区域的一部分中提供的芯片强度增强 靠近密封圈。 芯片强度加强件由多个虚拟布线结构构成，并且多个虚设布线结构中的每一个形成为跨越两个或更多个布线层中的两个或更多个布线层，包括最下面的布线层和最上面的布线层 使用通孔部分。

公开(公告)号：US20070220337A1

公开(公告)日：2007-09-20

申请号：US11717644

申请日：2007-03-14

申请人： Yutaka Itoh ,  Yasuhiro Nagira

发明人： Yutaka Itoh ,  Yasuhiro Nagira

IPC分类号： G06F11/00

CPC分类号： G06F11/321

摘要： A microcomputer includes: a memory; a CPU which decodes memory data stored in the memory to execute an instruction; a debug control section for instructing the microcomputer to perform a debug operation according to an instruction from an external debug instruction device which is connected to the microcomputer; and an authentication section for performing, when the external debug instruction device is connected to the microcomputer that is in a normal operation, an authentication as to whether to allow the debug operation to be performed, wherein the memory data of the memory is prevented from being read out to outside of the microcomputer during a period between connection of the external debug instruction device to the microcomputer and success of the authentication by the authentication section.

摘要翻译： 微型计算机包括：存储器; 对存储在存储器中的存储器数据进行解码以执行指令的CPU; 调试控制部分，用于指示微型计算机根据来自连接到微计算机的外部调试指令装置的指令执行调试操作; 以及认证部，用于当外部调试指令装置连接到正常操作的微型计算机时，执行关于是否允许执行调试操作的认证，其中防止存储器的存储器数据成为 在外部调试指令装置连接到微型计算机之间的期间和认证部分的认证成功的期间，读出到微计算机的外部。

公开(公告)号：US4296219A

公开(公告)日：1981-10-20

申请号：US5233

申请日：1979-01-22

申请人： Akio Takahashi ,  Yutaka Itoh ,  Motoyo Wajima ,  Hirosada Morishita ,  Akio Nishikawa

发明人： Akio Takahashi ,  Yutaka Itoh ,  Motoyo Wajima ,  Hirosada Morishita ,  Akio Nishikawa

IPC分类号： C07D207/44 ,  C07D207/448 ,  C08G73/12

CPC分类号： C07D207/448 ,  C08G73/121

摘要： A bisimide-ether compound having the general formula is obtained by reacting an ethylenically unsaturated dicarboxylic acid anhydride, a diamine compound and a phenolic compound having in the molecule at least two hydroxyl groups, or by reacting a prepolymer of the anhydride and diamine compound with the phenolic compound: ##STR1## wherein R.sub.1 is a group containing at least two carbon atoms, R.sub.2 is a group containing at least two carbon atoms, R'.sub.2 is a group containing at least two carbon atoms and a carbon-carbon double bond, R.sub.3 is an aromatic group, the nitrogen atoms of the imide rings being directly connected to different carbon atoms of the group R.sub.1, the carbonyl groups of the imide rings being directly connected to different carbon atoms of the group R.sub.2 or R'.sub.2, the oxygen atoms between the groups R.sub.2 and R.sub.3 being directly connected to an aromatic nucleus of the group R.sub.3, and n is an integer of zero, one or more than 1.

摘要翻译： 通过使烯键式不饱和二羧酸酐，二胺化合物和分子中至少两个羟基的酚类化合物反应，或者使酸酐与二胺化合物的预聚物与 酚类化合物：其中R1是含有至少两个碳原子的基团，R2是含有至少两个碳原子的基团，R'2是含有至少两个碳原子的基团和碳 - 碳双键，R3 是芳族基团，酰亚胺环的氮原子直接连接到基团R1的不同碳原子上，酰亚胺环的羰基直接连接到基团R 2或R'2的不同碳原子上，氧原子 在基团R 2和R 3直接连接到基团R 3的芳香环上，且n是0，1或1以上的整数。

公开(公告)号：US08237281B2

公开(公告)日：2012-08-07

申请号：US12984142

申请日：2011-01-04

申请人： Koji Takemura ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Masao Takahashi ,  Koji Koike

发明人： Koji Takemura ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Masao Takahashi ,  Koji Koike

IPC分类号： H01L23/495

CPC分类号： H01L23/585 ,  H01L21/76832 ,  H01L23/522 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.

摘要翻译： 一种半导体器件包括在半导体衬底上的层间绝缘膜中堆叠的至少三个或更多个布线层，设置在半导体衬底的芯片区域的外周处的密封环和在芯片区域的一部分中提供的芯片强度增强 靠近密封圈。 芯片强度加强件由多个虚拟布线结构构成，并且多个虚设布线结构中的每一个形成为跨越两个或更多个布线层中的两个或更多个布线层，包括最下面的布线层和最上面的布线层 使用通孔部分。

公开(公告)号：US08164163B2

公开(公告)日：2012-04-24

申请号：US12029969

申请日：2008-02-12

申请人： Koji Takemura ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Koji Koike

发明人： Koji Takemura ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Koji Koike

IPC分类号： H01L23/544

CPC分类号： H01L23/585 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.

摘要翻译： 半导体器件包括：形成在衬底上的层间绝缘膜; 在衬底的芯片区域中的层间绝缘膜中形成的布线; 密封环，形成在所述芯片区域的周围的所述层间绝缘膜中，并且连续地围绕所述芯片区域; 以及形成在其上形成有布线和密封环的层间绝缘膜上的第一保护膜。 当从芯片区域观察时，在位于密封环外侧的区域中的第一保护膜中形成第一开口，并且层间绝缘膜在第一开口中露出。

公开(公告)号：US20120025394A1

公开(公告)日：2012-02-02

申请号：US13191818

申请日：2011-07-27

申请人： Hiroshige Hirano ,  Yukitoshi Ota ,  Yutaka Itoh

发明人： Hiroshige Hirano ,  Yukitoshi Ota ,  Yutaka Itoh

IPC分类号： H01L23/48

CPC分类号： H01L21/76807 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05093 ,  H01L2224/05546 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/05624 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

摘要： A semiconductor device includes: a first insulating film formed on a substrate; a pad embedded in the first insulating film; and a second insulating film that is formed on the first insulating film and has an opening exposing at least part of the pad. The pad includes a plurality of pad interconnects, and an interconnect link is provided to electrically connect adjacent interconnects among the plurality of pad interconnects. The width of the pad interconnects is smaller than the height of the pad interconnects and larger than the width of the interconnect link.

摘要翻译： 半导体器件包括：形成在衬底上的第一绝缘膜; 嵌入在所述第一绝缘膜中的焊盘; 以及第二绝缘膜，其形成在所述第一绝缘膜上并具有暴露所述焊盘的至少一部分的开口。 焊盘包括多个焊盘互连，并且提供互连链路以电连接多个焊盘互连中的相邻互连。 焊盘互连的宽度小于焊盘互连的高度，并且大于互连链路的宽度。