公开(公告)号：US20120218246A1

公开(公告)日：2012-08-30

申请号：US13504074

申请日：2010-10-21

申请人： Naoki Ueda ,  Yoshimitsu Yamauchi ,  Fumiki Nakano

发明人： Naoki Ueda ,  Yoshimitsu Yamauchi ,  Fumiki Nakano

IPC分类号： G09G5/00

CPC分类号： G09G3/367 ,  G02F1/13624 ,  G09G3/3618 ,  G09G3/3655 ,  G09G3/3659 ,  G09G2300/0814 ,  G09G2300/0876

摘要： A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively. The diode D1 has a rectifying function from the source line SL to the internal node N1.

摘要翻译： 提供了一种在不降低开口率的情况下实现低功耗的显示装置。 液晶电容元件Clc被夹在像素电极20和相对电极80之间。像素电极20，第一开关电路22的一端，第二开关电路23的一端和第二晶体管T2的第一端 形成内部节点N1。 第一开关电路22和第二开关电路23的其他端子连接到源极线SL。 第二开关电路23是由第一晶体管T1和二极管D1组成的串联电路。 第一晶体管T1的控制端子，第二晶体管T2的第二端子和升压电容元件Cbst的一端形成输出节点N2。 升压电容元件Cbst的另一端和第二晶体管T2的控制端分别连接到升压线BST和基准线REF。 二极管D1具有从源极线SL到内部节点N1的整流功能。

公开(公告)号：US08654291B2

公开(公告)日：2014-02-18

申请号：US13504074

申请日：2010-10-21

申请人： Naoki Ueda ,  Yoshimitsu Yamauchi ,  Fumiki Nakano

发明人： Naoki Ueda ,  Yoshimitsu Yamauchi ,  Fumiki Nakano

IPC分类号： G02F1/1337

CPC分类号： G09G3/367 ,  G02F1/13624 ,  G09G3/3618 ,  G09G3/3655 ,  G09G3/3659 ,  G09G2300/0814 ,  G09G2300/0876

摘要： A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively. The diode D1 has a rectifying function from the source line SL to the internal node N1.

摘要翻译： 提供了一种在不降低开口率的情况下实现低功耗的显示装置。 液晶电容元件Clc被夹在像素电极20和相对电极80之间。像素电极20，第一开关电路22的一端，第二开关电路23的一端和第二晶体管T2的第一端 形成内部节点N1。 第一开关电路22和第二开关电路23的其他端子连接到源极线SL。 第二开关电路23是由第一晶体管T1和二极管D1组成的串联电路。 第一晶体管T1的控制端子，第二晶体管T2的第二端子和升压电容元件Cbst的一端形成输出节点N2。 升压电容元件Cbst的另一端和第二晶体管T2的控制端分别连接到升压线BST和基准线REF。 二极管D1具有从源极线SL到内部节点N1的整流功能。

公开(公告)号：US08310638B2

公开(公告)日：2012-11-13

申请号：US13504609

申请日：2010-07-22

申请人： Yoshimitsu Yamauchi ,  Naoki Ueda ,  Fumiki Nakano

发明人： Yoshimitsu Yamauchi ,  Naoki Ueda ,  Fumiki Nakano

IPC分类号： G02F1/1337

CPC分类号： G09G3/3659 ,  G02F1/13624 ,  G09G2300/0465 ,  G09G2300/0876 ,  G09G2300/089 ,  G09G2310/08 ,  G09G2330/021

摘要： Disclosed is a display device that can achieve a reduction of power consumption without deteriorating the aperture ratio. A liquid crystal capacitance element (Clc) is formed by being sandwiched between a pixel electrode (20) and an opposite electrode (80). The pixel electrode (20), one end of a first switching circuit (22), one end of a second switching circuit (23), and the first terminal of a second transistor (T2) form an internal node (N1). The other end of the first switching circuit (22) and the other end of the second switching circuit (23) are connected to a source line (SL). The second switching circuit (23) includes a series circuit of a transistor (T1) and a diode (D1), and an output node (N2) is formed of the control terminal of the transistor (T1), the second terminal of the transistor (T2), and one end of a boost capacitance element (Cbst). The other end of the boost capacitance element (Cbst) is connected to a boost line (BST), and the control terminal of the transistor (T2) is connected to a reference line (REF). The diode (D1) has a rectifying function in the direction to the internal node (N1) from the source line (SL).

摘要翻译： 公开了一种能够在不损害开口率的情况下实现功耗的降低的显示装置。 通过夹在像素电极（20）和相对电极（80）之间形成液晶电容元件（Clc）。 像素电极（20），第一开关电路（22）的一端，第二开关电路（23）的一端和第二晶体管（T2）的第一端子形成内部节点（N1）。 第一开关电路（22）的另一端和第二开关电路（23）的另一端连接到源极线（SL）。 第二开关电路（23）包括晶体管（T1）和二极管（D1）的串联电路，输出节点（N2）由晶体管（T1）的控制端子形成，晶体管的第二端子 （T2）和升压电容元件（Cbst）的一端。 升压电容元件（Cbst）的另一端连接到升压线（BST），晶体管（T2）的控制端子连接到基准线（REF）。 二极管（D1）在从源极线（SL）到内部节点（N1）的方向上具有整流功能。

公开(公告)号：US08947418B2

公开(公告)日：2015-02-03

申请号：US13989492

申请日：2011-10-05

申请人： Fumiki Nakano ,  Naoki Ueda ,  Yoshimitsu Yamauchi

发明人： Fumiki Nakano ,  Naoki Ueda ,  Yoshimitsu Yamauchi

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3618 ,  G09G3/3648 ,  G09G2300/0876 ,  G09G2300/088 ,  G09G2310/08

摘要： A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively. The diode D1 has a rectifying function from the source line SL to the internal node N1.

摘要翻译： 提供了一种在不降低开口率的情况下实现低功耗的显示装置。 液晶电容元件Clc被夹在像素电极20和相对电极80之间。像素电极20，第一开关电路22的一端，第二开关电路23的一端和第二晶体管T2的第一端 形成内部节点N1。 第一开关电路22和第二开关电路23的其他端子连接到源极线SL。 第二开关电路23是由第一晶体管T1和二极管D1组成的串联电路。 第一晶体管T1的控制端子，第二晶体管T2的第二端子和升压电容元件Cbst的一端形成输出节点N2。 升压电容元件Cbst的另一端和第二晶体管T2的控制端分别连接到升压线BST和基准线REF。 二极管D1具有从源极线SL到内部节点N1的整流功能。

公开(公告)号：US20130286001A1

公开(公告)日：2013-10-31

申请号：US13989492

申请日：2011-10-05

申请人： Fumiki Nakano ,  Naoki Ueda ,  Yoshimitsu Yamauchi

发明人： Fumiki Nakano ,  Naoki Ueda ,  Yoshimitsu Yamauchi

IPC分类号： G09G3/36

CPC分类号： G09G3/3618 ,  G09G3/3648 ,  G09G2300/0876 ,  G09G2300/088 ,  G09G2310/08

摘要： A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively. The diode D1 has a rectifying function from the source line SL to the internal node N1.

摘要翻译： 提供一种在不降低开口率的情况下实现低功耗的显示装置。 液晶电容元件Clc被夹在像素电极20和相对电极80之间。像素电极20，第一开关电路22的一端，第二开关电路23的一端和第二晶体管T2的第一端 形成内部节点N1。 第一开关电路22和第二开关电路23的其他端子连接到源极线SL。 第二开关电路23是由第一晶体管T1和二极管D1组成的串联电路。 第一晶体管T1的控制端子，第二晶体管T2的第二端子和升压电容元件Cbst的一端形成输出节点N2。 升压电容元件Cbst的另一端和第二晶体管T2的控制端分别连接到升压线BST和基准线REF。 二极管D1具有从源极线SL到内部节点N1的整流功能。

公开(公告)号：US20120212521A1

公开(公告)日：2012-08-23

申请号：US13504609

申请日：2010-07-22

申请人： Yoshimitsu Yamauchi ,  Naoki Ueda ,  Fumiki Nakano

发明人： Yoshimitsu Yamauchi ,  Naoki Ueda ,  Fumiki Nakano

IPC分类号： G09G3/36 ,  G09G5/02 ,  G09G5/00

CPC分类号： G09G3/3659 ,  G02F1/13624 ,  G09G2300/0465 ,  G09G2300/0876 ,  G09G2300/089 ,  G09G2310/08 ,  G09G2330/021

摘要： Disclosed is a display device that can achieve a reduction of power consumption without deteriorating the aperture ratio. A liquid crystal capacitance element (Clc) is formed by being sandwiched between a pixel electrode (20) and an opposite electrode (80). The pixel electrode (20), one end of a first switching circuit (22), one end of a second switching circuit (23), and the first terminal of a second transistor (T2) form an internal node (N1). The other end of the first switching circuit (22) and the other end of the second switching circuit (23) are connected to a source line (SL). The second switching circuit (23) includes a series circuit of a transistor (T1) and a diode (D1), and an output node (N2) is formed of the control terminal of the transistor (T1), the second terminal of the transistor (T2), and one end of a boost capacitance element (Cbst). The other end of the boost capacitance element (Cbst) is connected to a boost line (BST), and the control terminal of the transistor (T2) is connected to a reference line (REF). The diode (D1) has a rectifying function in the direction to the internal node (N1) from the source line (SL).

摘要翻译： 公开了一种能够在不损害开口率的情况下实现功耗的降低的显示装置。 通过夹在像素电极（20）和相对电极（80）之间形成液晶电容元件（Clc）。 像素电极（20），第一开关电路（22）的一端，第二开关电路（23）的一端和第二晶体管（T2）的第一端子形成内部节点（N1）。 第一开关电路（22）的另一端和第二开关电路（23）的另一端连接到源极线（SL）。 第二开关电路（23）包括晶体管（T1）和二极管（D1）的串联电路，输出节点（N2）由晶体管（T1）的控制端子形成，晶体管的第二端子 （T2）和升压电容元件（Cbst）的一端。 升压电容元件（Cbst）的另一端连接到升压线（BST），晶体管（T2）的控制端子连接到基准线（REF）。 二极管（D1）在从源极线（SL）到内部节点（N1）的方向上具有整流功能。

公开(公告)号：US08610197B2

公开(公告)日：2013-12-17

申请号：US13201584

申请日：2009-12-14

申请人： Naoki Ueda ,  Yoshimitsu Yamauchi

发明人： Naoki Ueda ,  Yoshimitsu Yamauchi

IPC分类号： H01L29/786 ,  H01L29/788

CPC分类号： H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

摘要： Provided is a nonvolatile memory 10 having a selective gate SG formed below a silicon layer 14, which is to be a channel region formed between a source region S and a drain region D of a transistor, through a gate insulating film 15 between the silicon layer and the selective gate, a floating gate FG formed on a part over the silicon layer 14 through a gate insulating film 16, and a control gate CG connected to the floating gate FG. The selective gate SG has one end overlapping the source region S through the gate insulating film 15, and the floating gate FG has one end overlapping the drain region D through the gate insulating film 16, and the other end separated from the source region S and overlapping the silicon layer 14 through the gate insulating film 16. Thus, a nonvolatile memory whose performance is not deteriorated even when it is formed on an insulating substrate having a low heat dissipating characteristic can be achieved.

摘要翻译： 提供了一种非易失性存储器10，其具有形成在作为在晶体管的源极区域S和漏极区域D之间形成的沟道区域的硅层14下方的选择栅极SG，通过硅层之间的栅极绝缘膜15 选择栅极，通过栅极绝缘膜16形成在硅层14上的部分上的浮置栅极FG，以及连接到浮置栅极FG的控制栅极CG。 选择栅极SG的一端通过栅极绝缘膜15与源极区域S重叠，并且浮置栅极FG的一端通过栅极绝缘膜16与漏极区域D重叠，另一端与源极区域S分离， 通过栅极绝缘膜16与硅层14重叠。因此，即使在具有低散热特性的绝缘基板上形成性能也不会劣化的非易失性存储器。

公开(公告)号：US20110303964A1

公开(公告)日：2011-12-15

申请号：US13201584

申请日：2009-12-14

申请人： Naoki Ueda ,  Yoshimitsu Yamauchi

发明人： Naoki Ueda ,  Yoshimitsu Yamauchi

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

摘要： Provided is a nonvolatile memory 10 having a selective gate SG formed below a silicon layer 14, which is to be a channel region formed between a source region S and a drain region D of a transistor, through a gate insulating film 15 between the silicon layer and the selective gate, a floating gate FG formed on a part over the silicon layer 14 through a gate insulating film 16, and a control gate CG connected to the floating gate FG. The selective gate SG has one end overlapping the source region S through the gate insulating film 15, and the floating gate FG has one end overlapping the drain region D through the gate insulating film 16, and the other end separated from the source region S and overlapping the silicon layer 14 through the gate insulating film 16. Thus, a nonvolatile memory whose performance is not deteriorated even when it is formed on an insulating substrate having a low heat dissipating characteristic can be achieved.

摘要翻译： 提供了一种非易失性存储器10，其具有形成在作为在晶体管的源极区域S和漏极区域D之间形成的沟道区域的硅层14下方的选择栅极SG，通过硅层之间的栅极绝缘膜15 选择栅极，通过栅极绝缘膜16形成在硅层14上的部分上的浮置栅极FG，以及连接到浮置栅极FG的控制栅极CG。 选择栅极SG的一端通过栅极绝缘膜15与源极区域S重叠，并且浮置栅极FG的一端通过栅极绝缘膜16与漏极区域D重叠，另一端与源极区域S分离， 通过栅极绝缘膜16与硅层14重叠。因此，即使在具有低散热特性的绝缘基板上形成性能也不会劣化的非易失性存储器。

公开(公告)号：US07630243B2

公开(公告)日：2009-12-08

申请号：US12094379

申请日：2006-11-01

申请人： Kaoru Yamamoto ,  Nobuhiko Ito ,  Naoki Ueda ,  Yoshimitsu Yamauchi

发明人： Kaoru Yamamoto ,  Nobuhiko Ito ,  Naoki Ueda ,  Yoshimitsu Yamauchi

IPC分类号： G11C16/04

CPC分类号： G11C16/0491 ,  G11C16/24 ,  G11C16/26

摘要： A virtual ground type semiconductor memory device comprises: a memory cell array in which nonvolatile memory cells each including a first electrode, a pair of second electrodes, and a charge retention part are arranged in row and column directions like a matrix; a read circuit for selecting a pair of the first and second bit lines connected to a selected memory cell to be read, applying first and second read voltages to the selected first and second bit lines, respectively, and detecting a magnitude of a memory cell current flowing in the selected memory cell, at the time of reading; a voltage applying means for applying the second read voltage to a second adjacent bit line adjacent to the selected second bit line on the opposite side of the first bit line; and a short-circuit means for short-circuiting the selected second bit line and the second adjacent bit line.

摘要翻译： 虚拟接地型半导体存储器件包括：存储单元阵列，其中包括第一电极，一对第二电极和电荷保持部分的非易失性存储单元排列成像矩阵的行和列方向; 读取电路，用于选择连接到要读取的所选择的存储器单元的一对第一和第二位线，将第一和第二读取电压分别施加到所选择的第一和第二位线，并且检测存储单元电流的大小 在读取时流入所选存储单元; 电压施加装置，用于将第二读取电压施加到与第一位线的相对侧上的所选择的第二位线相邻的第二相邻位线; 以及用于短路所选择的第二位线和第二相邻位线的短路装置。

公开(公告)号：US5282159A

公开(公告)日：1994-01-25

申请号：US896436

申请日：1992-06-10

申请人： Naoki Ueda ,  Yoshimitsu Yamauchi ,  Kenichi Tanaka

发明人： Naoki Ueda ,  Yoshimitsu Yamauchi ,  Kenichi Tanaka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L27/14

CPC分类号： H01L27/10808

摘要： A semiconductor memory includes a transistor and a capacitor which are formed on a semiconductor substrate, wherein the capacitor comprises in superposed layers a first capacitor composed of an impurity diffused layer formed in a surface layer of the semiconductor substrate, a first dielectric formed on the impurity diffused layer and a lower plate electrode formed on the first dielectric and serving as a field plate; a second capacitor composed of the lower plate electrode, a second dielectric formed on the lower plate electrode and a node electrode formed on the second dielectric; and a third capacitor composed of the node electrode, a third dielectric formed on the node electrode and an upper plate electrode formed on the third dielectric.

摘要翻译： 半导体存储器包括形成在半导体衬底上的晶体管和电容器，其中电容器在叠层中包括由在半导体衬底的表面层中形成的杂质扩散层构成的第一电容器，形成在杂质上的第一电介质 扩散层和形成在第一电介质上并用作场板的下板电极; 由下板电极构成的第二电容器，形成在下板电极上的第二电介质和形成在第二电介质上的节点电极; 以及由节点电极构成的第三电容器，形成在节点电极上的第三电介质和形成在第三电介质上的上板电极。