公开(公告)号：US20120170373A1

公开(公告)日：2012-07-05

申请号：US13341382

申请日：2011-12-30

申请人： Byung Ryul KIM ,  Duck Ju KIM ,  You Sung KIM

发明人： Byung Ryul KIM ,  Duck Ju KIM ,  You Sung KIM

IPC分类号： G11C16/10 ,  G11C16/06

CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C16/10

摘要： Programming a semiconductor memory device includes: performing a program loop using a blind program operation until the selected cell threshold voltages reach a first verification level; upon detecting a cell having the threshold voltage reaching the first verification level, verifying whether a cell having the threshold voltage reached a second verification level higher than the first verification level; upon verifying a cell having the threshold voltage reaching the second verification level, continuously performing program loops on cells having the first verification level as a target level and on cells having the second verification level as a target level; and upon verifying no cell having the threshold voltage reaching the second verification level, performing a program loop on memory cells having a target level higher than the first verification level, after programming the memory cells having the first verification level as the target level.

摘要翻译： 编程半导体存储器件包括：使用盲目程序操作执行程序循环，直到所选择的单元阈值电压达到第一验证水平; 一旦检测到阈值电压达到第一验证电平的单元，则验证具有阈值电压的单元是否达到高于第一验证电平的第二验证电平; 在验证具有阈值电压达到第二验证电平的单元的情况下，对具有第一验证电平的单元作为目标电平，以及具有第二验证电平的单元作为目标电平连续执行程序循环; 并且在验证没有阈值电压达到第二验证电平的单元时，在将具有第一验证电平的存储单元编程为目标电平之后，对具有高于第一验证电平的目标电平的存储单元执行程序循环。

公开(公告)号：US20090296478A1

公开(公告)日：2009-12-03

申请号：US12361195

申请日：2009-01-28

申请人： You Sung KIM ,  Byung Ryul Kim

发明人： You Sung KIM ,  Byung Ryul Kim

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641

摘要： In one aspect of the method of programming a nonvolatile memory device, memory cells selected for a program are determined to belong to a first memory cell group or a second memory cell group based on address information and a program command. According to this determination, to-be-programmed data are input based on information about the number of set data bits, and programming and verification are performed.

摘要翻译： 在非易失性存储器件编程方法的一个方面中，基于地址信息和程序命令，将为程序选择的存储单元确定为属于第一存储单元组或第二存储单元组。 根据该判断，根据关于设定数据位数的信息来输入被编程数据，进行编程和验证。

公开(公告)号：US20090168543A1

公开(公告)日：2009-07-02

申请号：US12119408

申请日：2008-05-12

申请人： You Sung KIM ,  Kwang Jun Cho

发明人： You Sung KIM ,  Kwang Jun Cho

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/3404

摘要： A method of operating a non-volatile memory device changes a read voltage by determining a degree that threshold voltages of memory cells are changed and overlap each other. The method of operating the non-volatile memory device includes performing a least significant bit (LSB) program of memory cells and determining a first error rate, performing a most significant bit (MSB) program of the memory cells and determining a second error rate, and setting a read voltage corresponding to a value at which the first and second error rates are minimum values.

摘要翻译： 操作非易失性存储器件的方法通过确定存储器单元的阈值电压改变并彼此重叠的程度来改变读取电压。 操作非易失性存储器件的方法包括执行存储器单元的最低有效位（LSB）程序并确定第一错误率，执行存储器单元的最高有效位（MSB）程序并确定第二错误率， 以及设定与第一误差率和第二误差率为最小值的值对应的读取电压。

公开(公告)号：US20100135077A1

公开(公告)日：2010-06-03

申请号：US12702213

申请日：2010-02-08

申请人： You Sung KIM ,  Duck Ju Kim

发明人： You Sung KIM ,  Duck Ju Kim

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5642

摘要： A method of performing a read operation in a flash memory device is disclosed. The flash memory has a memory cell array including at least one block, the block having a plurality of pages. The method comprises receiving a read command to read data from a selected page in the block; determining whether or not the block has any page that has not been programmed; performing a dummy data program operation on at least one page that is determined not to have been programmed; and executing the read command to read the data of the selected page after the dummy data program operation is completed.

公开(公告)号：US20090168535A1

公开(公告)日：2009-07-02

申请号：US12117702

申请日：2008-05-08

申请人： You Sung KIM ,  Tae Ho Shin

发明人： You Sung KIM ,  Tae Ho Shin

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/10

摘要： A non-volatile memory device includes a memory cell array and a controller. The memory cell array includes memory cells for data storage and a plurality of flag cells. The flag cells indicate program states of the memory cells for each of a plurality of word lines. The controller determines the program states of the memory cells by employing the flag cells and controls a pass voltage provided to a corresponding word line according to the determined program states.

摘要翻译： 非易失性存储器件包括存储单元阵列和控制器。 存储单元阵列包括用于数据存储的存储单元和多个标志单元。 标志单元表示多个字线中的每一个的存储单元的编程状态。 控制器通过采用标志单元来确定存储器单元的编程状态，并且根据所确定的程序状态控制提供给相应字线的通过电压。

公开(公告)号：US20120275222A1

公开(公告)日：2012-11-01

申请号：US13412892

申请日：2012-03-06

申请人： Sung Dae CHOI ,  You Sung KIM ,  Min Su KIM

发明人： Sung Dae CHOI ,  You Sung KIM ,  Min Su KIM

IPC分类号： G11C16/06

CPC分类号： G11C16/3459 ,  G11C16/04 ,  G11C29/52

摘要： A nonvolatile memory apparatus includes: a memory cell array including a plurality of unit memory cells; a page buffer unit configured to read data from a selected memory cell of the memory cell array and store the read data; a controller configured to generate a reference current generation signal, a first current control signal, and a second current control signal, which correspond to the number of fail bits to be sensed and a deviation in cell current amounts flowing through the unit memory cells during a read operation, in response to a verification command; and a fail bit sensing unit configured to receive the reference current generation signal, the first current control signal, and the second current control signal from the controller in response to the verification command, and control at least one of a reference current amount and a data read current amount of the page buffer unit.

摘要翻译： 非易失性存储装置包括：包括多个单位存储单元的存储单元阵列; 页缓冲器单元，被配置为从所述存储单元阵列的选定存储单元读取数据并存储所读取的数据; 控制器，其被配置为生成参考电流产生信号，第一电流控制信号和第二电流控制信号，其对应于待感测的故障位的数量和在一个 响应于验证命令读取操作; 以及故障位感测单元，被配置为响应于所述验证​​命令从所述控制器接收所述参考电流产生信号，所述第一电流控制信号和所述第二电流控制信号，并且控制参考电流量和数据中的至少一个 读取页面缓冲单元的当前量。

公开(公告)号：US20090225597A1

公开(公告)日：2009-09-10

申请号：US12400847

申请日：2009-03-10

申请人： Tao Ho SHIN ,  Joong Seob YANG ,  Jun Seop CHUNG ,  You Sung KIM

发明人： Tao Ho SHIN ,  Joong Seob YANG ,  Jun Seop CHUNG ,  You Sung KIM

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C8/00

CPC分类号： G11C16/0483 ,  G11C7/1006 ,  G11C16/10

摘要： A nonvolatile memory device includes a data conversion unit including an encoder and a decoder. The encoder sets data for each of word lines and creates second data to be programmed into a plurality of memory cells by performing a logical operation on the set data and first data input for programming. The decoder creates the first data by performing a logical operation on the second data that is read from the memory cells and the set data.

摘要翻译： 一种非易失性存储器件包括一个包括一个编码器和一个解码器的数据转换单元。 编码器为每个字线设置数据，并且通过对设置数据执行逻辑运算并将第一数据输入用于编程来创建要编程到多个存储器单元中的第二数据。 解码器通过对从存储器单元读取的第二数据和设置数据执行逻辑运算来创建第一数据。

公开(公告)号：US20080159012A1

公开(公告)日：2008-07-03

申请号：US11958377

申请日：2007-12-17

申请人： You Sung KIM

发明人： You Sung KIM

IPC分类号： G11C7/00

CPC分类号： G11C11/5621 ,  G11C2211/5641 ,  G11C2211/5642

摘要： The present invention relates to a semiconductor device including a MLC capable of storing plural bits of data, wherein some of the MLC are set and operated as a buffer section in response to a control signal.

摘要翻译： 本发明涉及包括能够存储多位数据的MLC的半导体器件，其中MLC中的一些响应于控制信号被设置和操作为缓冲器部分。

公开(公告)号：US20110080785A1

公开(公告)日：2011-04-07

申请号：US12968087

申请日：2010-12-14

申请人： You Sung KIM

发明人： You Sung KIM

IPC分类号： G11C11/34

CPC分类号： G11C11/5621 ,  G11C2211/5641 ,  G11C2211/5642

摘要： Multi-chip package devices and related data programming methods are disclosed. A multi-chip package device includes one or more memory chips and a controller. The one or more memory chips include a single level cell section and a multi level cell section. The controller is configured to control a first data storing operation for storing an input data to the single level cell section and control a second data storing operation for storing the input data stored in the single level section to the multi level cell section during an idle time.

摘要翻译： 公开了多芯片封装器件和相关数据编程方法。 多芯片封装器件包括一个或多个存储器芯片和控制器。 一个或多个存储器芯片包括单级单元部分和多级单元部分。 控制器被配置为控制用于将输入数据存储到单级单元部分的第一数据存储操作，并且在空闲时间期间控制用于将存储在单级部分中的输入数据存储到多级单元部分的第二数据存储操作 。

公开(公告)号：US20100142282A1

公开(公告)日：2010-06-10

申请号：US12702205

申请日：2010-02-08

申请人： You Sung KIM ,  Duck Ju KIM

发明人： You Sung KIM ,  Duck Ju KIM

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5642

摘要： A method of programming data in a flash memory device is disclosed. The memory device includes a memory cell array which in turn includes at least one block, and the block in turn includes a plurality of pages. A program command to program a plurality of pages in the block is received. The plurality of pages is programmed in a predefined order. An address corresponding to a page that was programmed last amongst the plurality of pages is stored.

摘要翻译： 公开了一种在闪速存储器件中编程数据的方法。 存储器件包括存储单元阵列，该存储单元阵列又包括至少一个块，并且该块又包括多个页。 接收用于对块中的多个页面进行编程的程序命令。 多个页面以预定义的顺序被编程。 存储与多个页面中最后编程的页面相对应的地址。