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公开(公告)号：US20060023138A1
公开(公告)日：2006-02-02
申请号：US11156476
申请日：2005-06-21
申请人： Young Choi , Byung Ahn , Hong Yu , Ki Cho
发明人： Young Choi , Byung Ahn , Hong Yu , Ki Cho
IPC分类号： G02F1/136
CPC分类号： G02F1/13458 , G02F1/1362 , G02F1/136213 , G02F2001/13629
摘要： Disclosed is an array substrate of an LCD, and a method for fabricating it, which simplifies the fabrication process, thereby reducing fabrication costs. The process is simplified because the array substrate does not have a passivation film. The thin film transistors on the array substrate each have an active layer that is protected from contamination by forming a channel insulation layer on the active layer through a dry-etching process. Further, the gate line, gate pad, and gate electrode may have a two-layer structure having a low-resistance metal layer and a barrier metal layer, or a three-layer structure having a low-resistance metal layer and two barrier metal layers.
摘要翻译： 公开了一种LCD的阵列基板及其制造方法，其简化了制造工艺，从而降低了制造成本。 由于阵列基板不具有钝化膜，所以该过程被简化。 阵列基板上的薄膜晶体管每个都具有通过干蚀刻工艺在有源层上形成沟道绝缘层而防止污染的有源层。 此外，栅极线，栅极焊盘和栅电极可以具有具有低电阻金属层和阻挡金属层的双层结构，或者具有低电阻金属层和两个势垒金属层的三层结构 。
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公开(公告)号：US20050285195A1
公开(公告)日：2005-12-29
申请号：US11149689
申请日：2005-06-10
申请人： Young Choi , Byung Ahn , Ki Cho , Hong Yu
发明人： Young Choi , Byung Ahn , Ki Cho , Hong Yu
IPC分类号： G02F1/136 , G02F1/1362 , G02F1/1368 , H01L21/00 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/01 , H01L27/12 , H01L27/146 , H01L29/417 , H01L29/786
CPC分类号： H01L29/41733 , G02F1/136209 , G02F2001/136236 , G02F2001/13629 , H01L27/12 , H01L27/1248 , H01L27/1288
摘要： A thin film transistor array substrate and a fabricating method thereof are disclosed. The thin film transistor array substrate protects a thin film transistor without a protective film and accordingly reduces the manufacturing cost. In the thin film transistor array substrate, a gate electrode is connected to a gate line. A source electrode is connected to a data line crossing the gate line to define a pixel area. A drain electrode is opposed to the source electrode with a channel therebetween. A semiconductor layer is in the channel. A pixel electrode in the pixel area contacts the drain electrode over substantially the entire overlapping area between the two. A channel protective film is provided on-the semiconductor layer corresponding to the channel to protect the semiconductor layer.
摘要翻译： 公开了薄膜晶体管阵列基板及其制造方法。 薄膜晶体管阵列基板保护薄膜晶体管而没有保护膜，从而降低制造成本。 在薄膜晶体管阵列基板中，栅电极连接到栅极线。 源电极连接到与栅极线交叉的数据线，以限定像素区域。 漏电极与源电极相对，其间具有沟道。 半导体层在通道中。 像素区域中的像素电极在两者之间的整个重叠区域上接触漏电极。 沟道保护膜设置在对应于沟道的半导体层上，以保护半导体层。
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公开(公告)号：US20070004069A1
公开(公告)日：2007-01-04
申请号：US11476427
申请日：2006-06-27
CPC分类号： H01L27/1288 , H01L27/1214 , Y10S438/95
摘要： A method of fabricating a liquid crystal display device includes performing a first mask process to form a gate line, a gate pad, and a gate electrode on a substrate. The method of fabricating a liquid crystal display device further includes performing a second mask process to form an active layer on the gate electrode, performing a third mask process to form a pixel electrode contacting the active layer, and performing a fourth mask process to form a source electrode and a drain electrode on the active layer.
摘要翻译： 制造液晶显示装置的方法包括：在基板上进行第一掩模处理以形成栅极线，栅极焊盘和栅电极。 制造液晶显示装置的方法还包括执行第二掩模处理以在栅电极上形成有源层，执行第三掩模处理以形成与活性层接触的像素电极，以及执行第四掩模处理以形成 源电极和有源层上的漏电极。
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公开(公告)号：US20060145155A1
公开(公告)日：2006-07-06
申请号：US11289503
申请日：2005-11-30
申请人： Young Choi , Hong Yu , Ki Cho , Jae Lee , Bo Jung
发明人： Young Choi , Hong Yu , Ki Cho , Jae Lee , Bo Jung
CPC分类号： H01L27/12 , H01L27/1248 , H01L27/1288 , H01L29/458
摘要： A TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line crossing the gate line to define a pixel region; a drain electrode which is opposite to the source electrode with a channel in between; a semiconductor layer defining the channel between the source electrode and the drain electrode; a pixel electrode in the pixel region and connected to the drain electrode; a channel passivation layer on the channel of the semiconductor layer; a gate pad extending from the gate line, where a semiconductor pattern and a transparent conductive pattern are formed; a data pad connected to the data line, where the transparent conductive pattern is formed; and a gate insulating layer formed under the semiconductor layer, the gate line and the gate pad, and the data line and the data pad.
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公开(公告)号：US20060145154A1
公开(公告)日：2006-07-06
申请号：US11289506
申请日：2005-11-30
申请人： Young Choi , Hong Yu , Ki Cho , Jae Lee , Bo Jung
发明人： Young Choi , Hong Yu , Ki Cho , Jae Lee , Bo Jung
IPC分类号： H01L31/0376
CPC分类号： G02F1/13458 , G02F2001/136236 , H01L27/1214 , H01L27/124 , H01L27/1255 , H01L27/1288
摘要： A TFT array substrate is provided. The TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line that crosses the gate line and defines a pixel region; a drain electrode facing the source electrode with a channel between; a semiconductor layer forming the channel in between the source electrode and the drain electrode; a pixel electrode in the pixel region and contacting the drain electrode; a channel passivation layer formed on the semiconductor layer; a gate pad with a gate pad lower electrode that extends from the gate line; and a data pad having a data pad lower electrode separated from the data line.
摘要翻译： 提供TFT阵列基板。 TFT阵列基板包括：栅极连接到栅极线; 源极连接到与栅极线交叉并限定像素区域的数据线; 面向源电极的漏电极，其间具有通道; 在源电极和漏电极之间形成沟道的半导体层; 像素区域中的像素电极并与漏电极接触; 形成在所述半导体层上的沟道钝化层; 栅极焊盘，其具有从栅极线延伸的栅极焊盘下部电极; 以及具有与数据线分离的数据焊盘下电极的数据焊盘。
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公开(公告)号：US20060145157A1
公开(公告)日：2006-07-06
申请号：US11316895
申请日：2005-12-27
申请人： Young Choi , Hong Yu , Ki Cho , Jae Lee , Bo Jung
发明人： Young Choi , Hong Yu , Ki Cho , Jae Lee , Bo Jung
IPC分类号： H01L29/76
CPC分类号： G02F1/13458 , G02F1/136213 , H01L27/124 , H01L27/1255 , H01L27/1288
摘要： A TFT array substrate is provided. The TFT array substrate includes a gate electrode connected to a gate line; a source electrode connected to a data line, the data line crossing the gate line to define a pixel region; a drain electrode facing the source electrode with a channel interposed therebetween; a semiconductor layer forming the channel between the source electrode and the drain electrode; a channel passivation layer formed on the channel to protect the semiconductor layer; a pixel electrode disposed in the pixel region to contact with the drain electrode; a storage capacitor including the pixel electrode extending over the gate line to form a storage area on a gate insulating layer on which a semiconductor layer pattern and a metal layer pattern are stacked; a gate pad extending from the gate line; and a data pad connected to the data line.
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公开(公告)号：US20060151858A1
公开(公告)日：2006-07-13
申请号：US11372597
申请日：2006-03-10
申请人： Byung Ahn , Jae Ku , Young Chung , Suk Ko , Sung Jang , Young Choi , Won Do
发明人： Byung Ahn , Jae Ku , Young Chung , Suk Ko , Sung Jang , Young Choi , Won Do
IPC分类号： H01L23/495
CPC分类号： H01L23/495 , H01L23/3107 , H01L23/49541 , H01L23/49548 , H01L24/48 , H01L24/73 , H01L2224/05599 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/484 , H01L2224/73265 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85464 , H01L2924/00014 , H01L2924/01002 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： Metal leadframes, semiconductor packages made using the leadframes, and methods of making the leadframes and packages are disclosed. In one embodiment, the leadframe includes a rectangular frame. A chip pad and a plurality of leads are within the frame. The lower side of the chip pad and the leads includes one or more vertically recessed horizontal surfaces. The upper side of the chip pad may include a groove around a chip mounting region. In a package, the chip pad supports a semiconductor chip electrically connected to the leads. The lower side of the chip pad and leads are exposed at an exterior surface of the package body. Encapsulant material underfills the recessed lower surfaces of the chip pad and leads, thereby locking them to the encapsulant material. A wire may be reliably bonded to the chip pad within the groove formed in the upper side thereof.
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公开(公告)号：US20050029638A1
公开(公告)日：2005-02-10
申请号：US09845601
申请日：2001-04-27
申请人： Byung Ahn , Jae Ku , Young Chung , Suk Ko , Sung Jang , Young Choi , Won Do
发明人： Byung Ahn , Jae Ku , Young Chung , Suk Ko , Sung Jang , Young Choi , Won Do
IPC分类号： H01L23/31 , H01L23/495
CPC分类号： H01L23/495 , H01L23/3107 , H01L23/49541 , H01L23/49548 , H01L24/48 , H01L24/73 , H01L2224/05599 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/484 , H01L2224/73265 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85464 , H01L2924/00014 , H01L2924/01002 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： Metal leadframes, semiconductor packages made using the leadframes, and methods of making the leadframes and packages are disclosed. In one embodiment, the leadframe includes a rectangular frame. A chip pad and a plurality of leads are within the frame. The lower side of the chip pad and the leads includes one or more vertically recessed horizontal surfaces. The upper side of the chip pad may include a groove around a chip mounting region. In a package, the chip pad supports a semiconductor chip electrically connected to the leads. The lower side of the chip pad and leads are exposed at an exterior surface of the package body. Encapsulant material underfills the recessed lower surfaces of the chip pad and leads, thereby locking them to the encapsulant material. A wire may be reliably bonded to the chip pad within the groove formed in the upper side thereof.
摘要翻译： 公开了使用引线框制造的金属引线框，半导体封装以及制造引线框和封装的方法。 在一个实施例中，引线框架包括矩形框架。 芯片焊盘和多个引线在框架内。 芯片焊盘的下侧和引线包括一个或多个垂直凹入的水平表面。 芯片焊盘的上侧可以包括围绕芯片安装区域的凹槽。 在封装中，芯片焊盘支撑与引线电连接的半导体芯片。 芯片焊盘的下侧和引线在封装体的外表面露出。 封装材料底部填充芯片焊盘和引线的凹陷的下表面，从而将它们锁定到密封材料上。 电线可以可靠地结合到在其上侧形成的槽内的芯片焊盘。
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公开(公告)号：USD619500S1
公开(公告)日：2010-07-13
申请号：US29346387
申请日：2009-10-30
申请人： Ricky Hsu , Young Choi , Guillermo A. Gonzalez
设计人： Ricky Hsu , Young Choi , Guillermo A. Gonzalez
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公开(公告)号：USD577320S1
公开(公告)日：2008-09-23
申请号：US29298845
申请日：2007-12-13
申请人： Young Choi , Roger Brown
设计人： Young Choi , Roger Brown
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