公开(公告)号：US11810867B2

公开(公告)日：2023-11-07

申请号：US17893725

申请日：2022-08-23

Applicant: Invensas LLC

Inventor： Abiola Awujoola ,  Zhuowen Sun ,  Wael Zohni ,  Ashok S. Prabhu ,  Willmar Subido

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L25/03 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L23/49811 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/215 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4942 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73227 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20754 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/2075 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/20751 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/20752 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/20753 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/20754 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/20755 ,  H01L2224/2919 ,  H01L2924/00014 ,  H01L2224/17051 ,  H01L2924/00012 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/131 ,  H01L2924/01322 ,  H01L2224/215 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05599

Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

公开(公告)号：US20190027444A1

公开(公告)日：2019-01-24

申请号：US16127110

申请日：2018-09-10

Applicant: Invensas Corporation

Inventor： Abiola Awujoola ,  Zhuowen Sun ,  Wael Zohni ,  Ashok S. Prabhu ,  Willmar Subido

IPC: H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L25/03 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L23/49811 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/215 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4942 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73227 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20754 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

公开(公告)号：US20180315737A1

公开(公告)日：2018-11-01

申请号：US16029188

申请日：2018-07-06

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/07 ,  H01L23/48 ,  H01L23/49 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49 ,  H01L23/528 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/96 ,  H01L25/07 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/207

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

公开(公告)号：US10083889B2

公开(公告)日：2018-09-25

申请号：US15597115

申请日：2017-05-16

Applicant: Panasonic Corporation

Inventor： Takashi Ichiryu ,  Koji Kawakita ,  Masanori Nomura

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/52 ,  H01L23/498

CPC classification number: H01L23/3121 ,  H01L21/4817 ,  H01L21/4839 ,  H01L21/4853 ,  H01L21/52 ,  H01L23/16 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/16245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2224/85455 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13055

Abstract: An electronic component package includes: a sealing resin layer; a metal member buried therein and including a die bond portion and a terminal electrode portion located outside the die bond portion; a ceramic substrate buried in the sealing resin layer; and an electronic component disposed on the die bond portion. When viewed in plan, the die bond portion and the ceramic substrate are partially overlapped to be in contact with each other, and the terminal electrode portion and the ceramic substrate are partially overlapped to be in contact with each other. The electronic component is electrically connected to the terminal electrode portion. The metal member includes a first plating layer and a second plating layer, and the average crystal grain diameter of the first plating layer is smaller than the average crystal grain diameter of the second plating layer.

公开(公告)号：US09887668B2

公开(公告)日：2018-02-06

申请号：US15259995

申请日：2016-09-08

Applicant: Skyworks Solutions, Inc.

Inventor： Peter J. Zampardi, Jr. ,  Hsiang-Chih Sun ,  Sandra Louise Petty-Weeks ,  Guohao Zhang ,  Hardik Bhupendra Modi

IPC: H03F3/14 ,  H03F1/02 ,  H03F3/19 ,  H03F3/21 ,  H03F3/213 ,  H03F3/195 ,  H03F3/24 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L29/36 ,  H01L29/66 ,  H01L29/737 ,  H01L29/812 ,  H01L29/08 ,  H01L29/205 ,  H01L21/8252 ,  H01L27/06 ,  H01L23/498 ,  H01L23/50 ,  H03F3/60 ,  H01L29/20 ,  H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/8249 ,  H01L21/66 ,  H01L23/31 ,  H01L21/768 ,  H03F3/187 ,  H03F3/347 ,  H03F1/56 ,  H01L29/8605 ,  H01L27/092 ,  H03F3/45 ,  H01L29/06 ,  H01L29/10

CPC classification number: H03F1/0205 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/4864 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/8249 ,  H01L21/8252 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/49861 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/522 ,  H01L23/552 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L27/0605 ,  H01L27/0623 ,  H01L27/092 ,  H01L29/0684 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/20 ,  H01L29/205 ,  H01L29/36 ,  H01L29/66242 ,  H01L29/66863 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/812 ,  H01L29/8605 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/665 ,  H01L2223/6655 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48177 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48611 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48811 ,  H01L2224/48816 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49176 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85411 ,  H01L2224/85416 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12033 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H03F1/565 ,  H03F3/187 ,  H03F3/19 ,  H03F3/195 ,  H03F3/21 ,  H03F3/213 ,  H03F3/245 ,  H03F3/347 ,  H03F3/45 ,  H03F3/60 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2200/48 ,  H03F2200/555 ,  H01L2924/00 ,  H01L2924/00014

Abstract: One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and an RF transmission line electrically coupled to an output of the power amplifier. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. The RF transmission line includes a nickel layer with a thickness that is less than 0.5 um, a conductive layer under the nickel layer, a palladium layer over the nickel layer, and a gold layer over the palladium layer. Other embodiments of the module are provided along with related methods and components thereof.

公开(公告)号：US20170323865A1

公开(公告)日：2017-11-09

申请号：US15659670

申请日：2017-07-26

Applicant: Infineon Technologies AG

Inventor： Manfred MENGEL ,  Alexander HEINRICH ,  Steffen ORSO ,  Thomas BEHRENS ,  Oliver EICHINGER ,  Lim FONG ,  Evelyn NAPETSCHNIG ,  Edmund RIEDL

IPC: H01L23/00 ,  B23K35/28 ,  B23K35/30 ,  C22C13/00 ,  C22C18/00 ,  C22C18/04 ,  C22C30/06 ,  H01L23/488 ,  H01L23/495 ,  B23K1/00 ,  C22C30/04 ,  B23K35/26

CPC classification number: H01L24/48 ,  B23K1/0016 ,  B23K35/262 ,  B23K35/282 ,  B23K35/3013 ,  C22C13/00 ,  C22C18/00 ,  C22C18/04 ,  C22C30/04 ,  C22C30/06 ,  H01L23/488 ,  H01L23/49513 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/05599 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/207

Abstract: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.

公开(公告)号：US09812402B2

公开(公告)日：2017-11-07

申请号：US15344990

申请日：2016-11-07

Applicant: Invensas Corporation

Inventor： Abiola Awujoola ,  Zhuowen Sun ,  Wael Zohni ,  Ashok S. Prabhu ,  Willmar Subido

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L23/49811 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/215 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4942 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73227 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

公开(公告)号：US09799580B2

公开(公告)日：2017-10-24

申请号：US15079276

申请日：2016-03-24

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Li Li ,  Jaynal A. Molla ,  Lakshminarayan Viswanathan

IPC: H01L23/34 ,  H01L23/047 ,  H01L21/56 ,  H01L21/52 ,  H01L21/50 ,  H01L23/373 ,  H01L23/00 ,  H01L21/603 ,  H01L21/60

CPC classification number: H01L23/047 ,  H01L21/50 ,  H01L21/52 ,  H01L21/566 ,  H01L23/3157 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/4334 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2021/60277 ,  H01L2021/603 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29393 ,  H01L2224/29399 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/8384 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2924/16195 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/00

Abstract: A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.

公开(公告)号：US09748197B2

公开(公告)日：2017-08-29

申请号：US15192760

申请日：2016-06-24

Applicant: Altera Corporation

Inventor： Loon Kwang Tan ,  Yuanlin Xie ,  Ping Chet Tan

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/683 ,  H01L23/36 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/73 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2221/68372 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/1624 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/3224 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/83005 ,  H01L2224/83851 ,  H01L2224/85005 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85664 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92247 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/364 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.

公开(公告)号：US20170103905A1

公开(公告)日：2017-04-13

申请号：US14877467

申请日：2015-10-07

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： NAVAS KHAN ORATTI KALANDAR ,  NISHANT LAKHERA ,  AKHILESH K. SINGH

IPC: H01L21/56 ,  H01L21/78

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L21/78 ,  H01L23/16 ,  H01L23/295 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/8546 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00

Abstract: A method of fabricating a plurality of semiconductor devices includes attaching a plurality of integrated circuit (IC) die to a substrate including forming electric connections between contacts on the IC die and contacts on the substrate. After the IC die is attached to the substrate, a first encapsulating material is placed over stress-sensitive areas of the IC die. The first encapsulating material includes thirty percent or less of filler particles greater than a specified size. A second encapsulating material is placed over the first encapsulating material. The second encapsulating material includes sixty percent or more of filler particles.