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公开(公告)号：US08604845B2
公开(公告)日：2013-12-10
申请号：US13488337
申请日：2012-06-04
申请人： Hui Dong Lee , Jaewon Nam , Young Kyun Cho , Jong-Kee Kwon , Yil Suk Yang , Jongdae Kim
发明人： Hui Dong Lee , Jaewon Nam , Young Kyun Cho , Jong-Kee Kwon , Yil Suk Yang , Jongdae Kim
IPC分类号： H03K4/06
CPC分类号： H03K4/501
摘要： Disclosed is a triangular wave generator which includes a square wave signal generating unit configured to output a first signal transitioning to a high level from a low level via an output terminal in response to a first transition of a clock signal and to transition the first signal to a low level from a high level in response to a reset signal; a resistance unit configured to adjust a voltage level of a the square wave signal; and a capacitance unit configured to receive an output signal of the resistance unit to generate a second signal rising to a high level from a low level with a slope, to provide the reset signal to the square wave signal generating unit, and to output a triangular signal by falling the second signal to a low level from a high level with a slope.
摘要翻译： 公开了一种三角波发生器，其包括方波信号生成单元，其被配置为响应于时钟信号的第一转换，经由输出端子输出从低电平转换到高电平的第一信号，并且将第一信号转换为 响应于复位信号从高电平的低电平; 电阻单元，被配置为调整所述方波信号的电压电平; 以及电容单元，被配置为接收电阻单元的输出信号，以产生从具有斜率的低电平上升到高电平的第二信号，以将复位信号提供给方波信号生成单元，并输出三角形 通过从具有斜率的高电平将第二信号降低到低电平来产生信号。
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公开(公告)号：US20130027094A1
公开(公告)日：2013-01-31
申请号：US13488337
申请日：2012-06-04
申请人： Hui Dong LEE , Jaewon Nam , Young Kyun Cho , Jong-Kee Kwon , Yil Suk Yang , Jongdae Kim
发明人： Hui Dong LEE , Jaewon Nam , Young Kyun Cho , Jong-Kee Kwon , Yil Suk Yang , Jongdae Kim
IPC分类号： H03K4/06
CPC分类号： H03K4/501
摘要： Disclosed is a triangular wave generator which includes a square wave signal generating unit configured to output a first signal transitioning to a high level from a low level via an output terminal in response to a first transition of a clock signal and to transition the first signal to a low level from a high level in response to a reset signal; a resistance unit configured to adjust a voltage level of a the square wave signal; and a capacitance unit configured to receive an output signal of the resistance unit to generate a second signal rising to a high level from a low level with a slope, to provide the reset signal to the square wave signal generating unit, and to output a triangular signal by falling the second signal to a low level from a high level with a slope.
摘要翻译： 公开了一种三角波发生器，其包括方波信号生成单元，其被配置为响应于时钟信号的第一转换，经由输出端子输出从低电平转换到高电平的第一信号，并且将第一信号转换为 响应于复位信号从高电平的低电平; 电阻单元，被配置为调整所述方波信号的电压电平; 以及电容单元，被配置为接收电阻单元的输出信号，以产生从具有斜率的低电平上升到高电平的第二信号，以将复位信号提供给方波信号生成单元，并输出三角形 通过从具有斜率的高电平将第二信号降低到低电平来产生信号。
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公开(公告)号：US09490734B2
公开(公告)日：2016-11-08
申请号：US13443823
申请日：2012-04-10
申请人： Jaewon Nam , Young Kyun Cho , Hui Dong Lee , Yil Suk Yang , Jong-Kee Kwon , Jongdae Kim
发明人： Jaewon Nam , Young Kyun Cho , Hui Dong Lee , Yil Suk Yang , Jong-Kee Kwon , Jongdae Kim
摘要： A motor control device including a preprocessing portion calculating a counter electromotive force using an analog operation is provided. The motor control device may include an offset compensation portion and a counter electromotive force measuring portion. The offset compensation portion receives a three-phase current signal from the motor and compensates an offset of the three-phase current signal. The counter electromotive force measuring portion receives the compensated current signal and a three-phase voltage signal from the motor and calculates the received current signal and the received voltage signal using an analog operation to provide the calculated result.
摘要翻译： 提供了一种包括使用模拟操作来计算反电动势的预处理部分的电动机控制装置。 马达控制装置可以包括偏移补偿部分和反电动势测量部分。 偏移补偿部分接收来自马达的三相电流信号，并补偿三相电流信号的偏移。 反电动势测量部分接收来自电动机的补偿的电流信号和三相电压信号，并使用模拟操作来计算接收的电流信号和接收的电压信号，以提供计算结果。
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4.发明授权Sensorless BLDC motor systems and driving methods of sensorless BLDC motor 有权无传感器BLDC电机系统和无传感器BLDC电机的驱动方法公开(公告)号：US08836259B2
公开(公告)日：2014-09-16
申请号：US13347128
申请日：2012-01-10
申请人： Young Kyun Cho , Hui Dong Lee , Jaewon Nam , Jong-Kee Kwon
发明人： Young Kyun Cho , Hui Dong Lee , Jaewon Nam , Jong-Kee Kwon
摘要： Provided is a sensorless BLDC motor system. The sensorless BLDC motor system includes a BLDC motor, a comparator, a motor controller, a three-phase inverter, and a mode selector. The BLDC motor includes first to third coils. The comparator compares a voltage of a specific coil of the first to third coils with a neutral-point voltage to output the compared result. The voltage of the specific coil becomes equal to the neutral-point voltage and a specific time elapses, and then the motor controller generates first and second coil control signals based on the compared result. The three-phase inverter supplies a source voltage or ground voltage to the specific coil, or floats the specific coil, in response to the first and second coil control signals. The mode selector selects a driving mode of the BLDC motor by adjusting the specific time.
摘要翻译： 提供无传感器BLDC电机系统。 无传感器BLDC电机系统包括BLDC电机，比较器，电机控制器，三相逆变器和模式选择器。 BLDC电机包括第一至第三线圈。 比较器将第一至第三线圈的特定线圈的电压与中性点电压进行比较，以输出比较结果。 特定线圈的电压等于中性点电压，经过一定时间，然后电机控制器根据比较结果产生第一和第二线圈控制信号。 三相逆变器响应于第一和第二线圈控制信号向特定线圈提供源极电压或接地电压，或者浮动特定线圈。 模式选择器通过调整具体时间来选择BLDC电机的驱动模式。
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公开(公告)号：US08362938B2
公开(公告)日：2013-01-29
申请号：US12982531
申请日：2010-12-30
申请人： Young Kyun Cho , Young-deuk Jeon , Jaewon Nam , Jong-Kee Kwon
发明人： Young Kyun Cho , Young-deuk Jeon , Jaewon Nam , Jong-Kee Kwon
IPC分类号： H03M1/12
摘要： Provided is an analog digital converting device which consumes a low power and guarantees fast operation characteristic. The analog digital converting device includes a sub-ADC and a successive approximation ADC. The sub-ADC converts an external analog signal into a first digital signal by using first and second reference voltages. The successive approximation ADC comprises a plurality of bit streams, and converts the external analog signal into a second digital signal according to a successive approximation operation using the first and second reference voltages. The successive approximation ADC receives the first digital signal, and converts the second digital signal in a state where one of the first and second reference voltages has been applied to the bit streams based on the first digital signal.
摘要翻译： 提供了一种消耗低功耗并保证快速操作特性的模拟数字转换装置。 模拟数字转换装置包括子ADC和逐次逼近ADC。 子ADC通过使用第一和第二参考电压将外部模拟信号转换为第一数字信号。 逐次逼近ADC包括多个比特流，并且根据使用第一和第二参考电压的逐次逼近操作将外部模拟信号转换为第二数字信号。 逐次逼近ADC接收第一数字信号，并且在第一和第二参考电压中的一个被基于第一数字信号施加到比特流的状态下转换第二数字信号。
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公开(公告)号：US20120062406A1
公开(公告)日：2012-03-15
申请号：US12982531
申请日：2010-12-30
申请人： Young Kyun Cho , Young-deuk Jeon , Jaewon Nam , Jong-Kee Kwon
发明人： Young Kyun Cho , Young-deuk Jeon , Jaewon Nam , Jong-Kee Kwon
摘要： Provided is an analog digital converting device which consumes a low power and guarantees fast operation characteristic. The analog digital converting device includes a sub-ADC and a successive approximation ADC. The sub-ADC converts an external analog signal into a first digital signal by using first and second reference voltages. The successive approximation ADC comprises a plurality of bit streams, and converts the external analog signal into a second digital signal according to a successive approximation operation using the first and second reference voltages. The successive approximation ADC receives the first digital signal, and converts the second digital signal in a state where one of the first and second reference voltages has been applied to the bit streams based on the first digital signal.
摘要翻译： 提供了一种消耗低功耗并保证快速操作特性的模拟数字转换装置。 模拟数字转换装置包括子ADC和逐次逼近ADC。 子ADC通过使用第一和第二参考电压将外部模拟信号转换为第一数字信号。 逐次逼近ADC包括多个比特流，并且根据使用第一和第二参考电压的逐次逼近操作将外部模拟信号转换为第二数字信号。 逐次逼近ADC接收第一数字信号，并且在第一和第二参考电压中的一个被基于第一数字信号施加到比特流的状态下转换第二数字信号。
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公开(公告)号：US08564469B2
公开(公告)日：2013-10-22
申请号：US13309872
申请日：2011-12-02
申请人： Jaewon Nam , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
发明人： Jaewon Nam , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
IPC分类号： H03M1/38
摘要： A pipelined analog-to-digital converter includes a digital correction circuit configured to improve the complexity of a logic circuit for dividing a correction period and a no-correction period of a digital output. The pipelined analog-to-digital converter performs a logic correction operation via binary shifting at data error correction. Accordingly, although the resolution increases, it is possible to reduce the complexity and area of a logic circuit.
摘要翻译： 流水线模数转换器包括数字校正电路，其被配置为提高用于划分校正周期和数字输出的无校正周期的逻辑电路的复杂度。 流水线模数转换器通过数据纠错的二进制移位执行逻辑校正操作。 因此，虽然分辨率增加，但是可以降低逻辑电路的复杂性和面积。
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公开(公告)号：US08531328B2
公开(公告)日：2013-09-10
申请号：US13243267
申请日：2011-09-23
申请人： Young-deuk Jeon , Young Kyun Cho , Jaewon Nam , Jong-Kee Kwon
发明人： Young-deuk Jeon , Young Kyun Cho , Jaewon Nam , Jong-Kee Kwon
IPC分类号： H03M1/12
摘要： Provided is an analog digital converter (ADC). The ADC includes: a capacitor array generating a level voltage; a comparator outputting a compare signal by comparing the level voltage; and a logic circuit determining digital bits of an analog signal based on the compare signal, wherein the logic circuit determines at least one digital bit among digital bits of the analog signal while a sampling operation of the analog signal is performed in the capacitor array.
摘要翻译： 提供了一种模拟数字转换器（ADC）。 ADC包括：产生电平电压的电容器阵列; 比较器，通过比较电平电压输出比较信号; 以及逻辑电路，其基于所述比较信号确定模拟信号的数字位，其中所述逻辑电路在所述电容器阵列中执行所述模拟信号的采样操作时，确定所述模拟信号的数字位中的至少一个数字位。
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公开(公告)号：US08508392B2
公开(公告)日：2013-08-13
申请号：US13243629
申请日：2011-09-23
申请人： Jaewon Nam , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
发明人： Jaewon Nam , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
IPC分类号： H03M1/06
摘要： Disclosed is a pipelined analog-to-digital converter which includes a digital correction circuit configured to measure and correct a pipelined conversion stage gain error and an offset error due to a finite voltage gain operational amplifier and capacitor mismatch. The pipelined analog-to-digital converter includes a pipelined conversion stage error measuring and correcting circuit measuring and correcting an error generated from an conversion stage, so that an error of a conversion stage is minimized and a chip realization area and power consumption are reduced.
摘要翻译： 公开了一种流水线模数转换器，其包括数字校正电路，其被配置为测量和校正流水线转换级增益误差以及由于有限电压增益运算放大器和电容器失配引起的偏移误差。 流水线模数转换器包括流水线转换级误差测量和校正电路，测量和校正从转换级产生的误差，使得转换级的误差最小化，并且芯片实现面积和功耗降低。
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公开(公告)号：US08692702B2
公开(公告)日：2014-04-08
申请号：US13615052
申请日：2012-09-13
申请人： Jaewon Nam , Young Kyun Cho , Yil Suk Yamg
发明人： Jaewon Nam , Young Kyun Cho , Yil Suk Yamg
IPC分类号： H03M1/34
摘要： Disclosed is an analog-digital converter which includes a pre-amplifier configured to output a comparison result between a sampled analog input signal and a reference signal and to control a power supply operation in response to a power control signal; a digital signal processor configured to generate a digital signal based on the comparison result; a power controller configured to generate an amplifier operation clock signal for controlling the pre-amplifier; and a counter configured to count the number of falling edges of the amplifier operation clock signal and to detect a power interruption point of time of the pre-amplifier according to the counted falling edge number. The power controller generates the power control signal for interrupting a power to be supplied to the pre-amplifier when the power interruption point of time of the pre-amplifier is detected.
摘要翻译： 公开了一种模拟数字转换器，其包括：前置放大器，其被配置为输出采样的模拟输入信号和参考信号之间的比较结果，并且响应于功率控制信号来控制电源操作; 配置为基于所述比较结果生成数字信号的数字信号处理器; 功率控制器，被配置为产生用于控制前置放大器的放大器操作时钟信号; 以及计数器，被配置为对放大器操作时钟信号的下降沿的数量进行计数，并根据计数的下降沿数检测前置放大器的电源中断时间点。 当检测到前置放大器的电源中断时间点时，功率控制器产生用于中断提供给前置放大器的电力的功率控制信号。
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