摘要:
A static CAM includes a plurality of entries E each including a number of CAM cells B and a summary S. Each CAM cell B is associated with a memory cell M and a comparator C. Generally, the CAM receives as input i number of lookup data lines. When data is received, memory cells M provide compared data for corresponding comparators C in CAM cells B to compare the compared data to the received data. If all compared data match all received data lines for an entry, then there is a hit for that entry. But if any compared data does not match the corresponding data line, then there is a miss for that line and therefore a miss for that entry. Depending on applications, the CAM returns an address if there is a hit for one or a plurality of entries.
摘要:
A memory includes a plurality of content-addressable memory (CAM) cells and a summary circuit associated with the plurality of CAM cells. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates.
摘要:
A method of designing a content-addressable memory (CAM) includes associating CAM cells with a summary circuit. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates. Logic gates in at least one of the first level of logic gates or the second level of logic gates are selected to have an odd number of input pins so that an input pin and an output pin share a layout sub-slot.
摘要:
A circuit includes a word line driver for driving a world line and a tracking word line driver for driving a tracking word line. The pulse width of a world line signal on the world line is driven to be larger than that of a tracking world line signal on the tracking world line to assist writing under difficult conditions. Because the tracking word line signal is activated later than the word line signal being activated but is deactivated at the same time with the word line, the pulse width of the word line signal is larger.
摘要:
A separation, purification and recovery method of SF6, HFCs or PFCs is disclosed, which comprises a step for forming a gas hydrate including components in addition to SF6, HFCs or PFCs. It is possible to separate and recover fluoro-gas at a much lower cost as compared to a conventional method for thereby obtaining an economical effect and preventing an emission of SF6, HFCs or PFCs which corresponds to Non-CO2 having a higher earth warming index, which leads to preventing an earth warming phenomenon. So, the present invention might be widely applied.
摘要:
Some embodiments regard a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein a column of the plurality of columns includes a column ground node; at least two voltage sources configured to be selectively coupled to the column ground node; and a plurality of memory cells having a plurality of internal ground nodes electrically coupled together and to the column ground node.
摘要:
A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.
摘要:
A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers. A first plurality of sector switches each are electrically coupled between the first current limiter and a respective one of the first plurality of keepers.
摘要:
A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, and a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes are electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.
摘要:
A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.