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    Methods of manufacturing semiconductor devices having a recessed-channel
    1.
    发明授权
    Methods of manufacturing semiconductor devices having a recessed-channel 有权
    制造具有凹槽的半导体器件的方法

    公开(公告)号：US08119486B2

    公开(公告)日：2012-02-21

    申请号：US12984176

    申请日：2011-01-04

    申请人： Young-Pil Kim ,  Eun-Ae Chung ,  Gab-Jin Nam ,  Hee-Don Hwang ,  Ji-Young Min

    发明人： Young-Pil Kim ,  Eun-Ae Chung ,  Gab-Jin Nam ,  Hee-Don Hwang ,  Ji-Young Min

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10876 ,  H01L29/66628

    摘要： A method according to example embodiments includes forming isolation regions in a substrate, the isolation regions defining active regions. Desired regions of the active regions and the isolation regions are removed, thereby forming recess channel trenches to a desired depth. The recess channel trenches are fog to have a first region in contact with the active regions and a second region in contact with the isolation regions. A width of a bottom surface of the recess channel trenches is less than that of a top surface thereof. The active regions and the isolation regions are annealed to uplift the bottom surface of the recess channel trenches. An area of the bottom surface of the first region is increased. A depth of the bottom surface of the first region is reduced.

    摘要翻译： 根据示例实施例的方法包括在衬底中形成隔离区域，所述隔离区限定活性区域。 去除有源区域和隔离区域的期望区域，从而形成凹槽沟槽到期望的深度。 凹槽沟槽是雾化的，以具有与活性区域接触的第一区域和与隔离区域接触的第二区域。 凹槽沟槽的底面的宽度小于其顶面的宽度。 有源区域和隔离区域被退火以提高凹槽通道沟槽的底面。 第一区域的底面的面积增加。 第一区域的底面的深度减小。

    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING A RECESSED-CHANNEL
    2.
    发明申请
    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING A RECESSED-CHANNEL 有权
    制造具有接收通道的半导体器件的方法

    公开(公告)号：US20110201168A1

    公开(公告)日：2011-08-18

    申请号：US12984176

    申请日：2011-01-04

    申请人： Young-Pil Kim ,  Eun-Ae Chung ,  Gab-Jin Nam ,  Hee-Don Hwang ,  Ji-Young Min

    发明人： Young-Pil Kim ,  Eun-Ae Chung ,  Gab-Jin Nam ,  Hee-Don Hwang ,  Ji-Young Min

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10876 ,  H01L29/66628

    摘要： A method according to example embodiments includes forming isolation regions in a substrate, the isolation regions defining active regions. Desired regions of the active regions and the isolation regions are removed, thereby forming recess channel trenches to a desired depth. The recess channel trenches are fog to have a first region in contact with the active regions and a second region in contact with the isolation regions. A width of a bottom surface of the recess channel trenches is less than that of a top surface thereof. The active regions and the isolation regions are annealed to uplift the bottom surface of the recess channel trenches. An area of the bottom surface of the first region is increased. A depth of the bottom surface of the first region is reduced.

    摘要翻译： 根据示例实施例的方法包括在衬底中形成隔离区域，所述隔离区限定活性区域。 去除有源区域和隔离区域的期望区域，从而形成凹槽沟槽到期望的深度。 凹槽沟槽是雾化的，以具有与活性区域接触的第一区域和与隔离区域接触的第二区域。 凹槽沟槽的底面的宽度小于其顶面的宽度。 有源区域和隔离区域被退火以提高凹槽通道沟槽的底面。 第一区域的底面的面积增加。 第一区域的底面的深度减小。

    RECESS GATE TRANSISTOR
    4.
    发明申请
    RECESS GATE TRANSISTOR 有权
    记忆闸门晶体管

    公开(公告)号：US20090173994A1

    公开(公告)日：2009-07-09

    申请号：US12251054

    申请日：2008-10-14

    申请人： Ji-Young Min ,  Si-Hyung Lee ,  Heedon Hwang ,  Si-Young Choi ,  Sangbom Kang ,  Dongsoo Woo

    发明人： Ji-Young Min ,  Si-Hyung Lee ,  Heedon Hwang ,  Si-Young Choi ,  Sangbom Kang ,  Dongsoo Woo

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66553 ,  H01L21/28079 ,  H01L21/28114 ,  H01L29/4236

    摘要： A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to the polysilicon layer and spaced from the metal layer. A method of forming a semiconductor device is also provided, comprising forming a substrate and a source and drain layer; forming a recess and depositing a gate insulation layer therein; forming a first conductive layer on the gate insulation layer; forming a first conductive layer pattern by recessing the first conductive layer; forming a second conductive layer on the first conductive layer pattern; forming a second conductive layer pattern by patterning the second conductive layer to overlap the source and drain layer; depositing an insulating layer on the second conductive layer pattern and the source and drain layer; and planarizing the insulating layer to form a cap on the second conductive layer pattern.

    摘要翻译： 提供半导体器件的凹槽，其包括：形成有凹部的基板; 形成在所述凹部的底部的金属层; 形成在所述金属层上的多晶硅层; 以及与所述多晶硅层相邻形成并与所述金属层隔开形成的源极区域和漏极区域。 还提供了一种形成半导体器件的方法，包括形成衬底和源极和漏极层; 形成凹部并在其中沉积栅极绝缘层; 在所述栅绝缘层上形成第一导电层; 通过使所述第一导电层凹陷来形成第一导电层图案; 在所述第一导电层图案上形成第二导电层; 通过图案化所述第二导电层以与所述源极和漏极层重叠而形成第二导电层图案; 在第二导电层图案和源极和漏极层上沉积绝缘层; 并且平坦化绝缘层以在第二导电层图案上形成帽。

    Recess gate transistor
    5.
    发明授权
    Recess gate transistor 有权
    凹槽门晶体管

    公开(公告)号：US08012828B2

    公开(公告)日：2011-09-06

    申请号：US12251054

    申请日：2008-10-14

    申请人： Ji-Young Min ,  Si-Hyung Lee ,  Heedon Hwang ,  Si-Young Choi ,  Sangbom Kang ,  Dongsoo Woo

    发明人： Ji-Young Min ,  Si-Hyung Lee ,  Heedon Hwang ,  Si-Young Choi ,  Sangbom Kang ,  Dongsoo Woo

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66553 ,  H01L21/28079 ,  H01L21/28114 ,  H01L29/4236

    摘要： A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to the polysilicon layer and spaced from the metal layer. A method of forming a semiconductor device is also provided, comprising forming a substrate and a source and drain layer; forming a recess and depositing a gate insulation layer therein; forming a first conductive layer on the gate insulation layer; forming a first conductive layer pattern by recessing the first conductive layer; forming a second conductive layer on the first conductive layer pattern; forming a second conductive layer pattern by patterning the second conductive layer to overlap the source and drain layer; depositing an insulating layer on the second conductive layer pattern and the source and drain layer; and planarizing the insulating layer to form a cap on the second conductive layer pattern.

    摘要翻译： 提供半导体器件的凹槽，其包括：形成有凹部的基板; 形成在所述凹部的底部的金属层; 形成在所述金属层上的多晶硅层; 以及与所述多晶硅层相邻形成并与所述金属层隔开形成的源极区域和漏极区域。 还提供了一种形成半导体器件的方法，包括形成衬底和源极和漏极层; 形成凹部并在其中沉积栅极绝缘层; 在所述栅绝缘层上形成第一导电层; 通过使所述第一导电层凹陷来形成第一导电层图案; 在所述第一导电层图案上形成第二导电层; 通过图案化所述第二导电层以与所述源极和漏极层重叠而形成第二导电层图案; 在第二导电层图案和源极和漏极层上沉积绝缘层; 并且平坦化绝缘层以在第二导电层图案上形成帽。