公开(公告)号：US5923063A

公开(公告)日：1999-07-13

申请号：US26358

申请日：1998-02-19

申请人： Yowjuang W. Liu ,  Donald L. Wollesen ,  John T. Yue

发明人： Yowjuang W. Liu ,  Donald L. Wollesen ,  John T. Yue

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/76 ,  H01L29/792 ,  H01L29/88

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： Floating gates of nonvolatile memory cells are formed in pairs within a pyramidal or truncated pyramidal opening in a semiconductor layer between a top surface thereof and a heavily doped source region spaced from the surface of the semiconductor layer. The floating gates control the conductance of channel regions formed along the sloped sidewalls of the pyramidal openings between surface drains and the buried source region.

摘要翻译： 非易失性存储单元的浮动栅极在其顶表面和与半导体层的表面间隔开的重掺杂源极区域之间的半导体层内的金字塔形或截锥形金字塔形开口内成对形成。 浮动栅极控制沿着表面排水沟和埋入源区域之间的锥体开口的倾斜侧壁形成的沟道区的电导。

公开(公告)号：US06667227B1

公开(公告)日：2003-12-23

申请号：US09574695

申请日：2000-05-17

申请人： Yowjuang W. Liu ,  Donald L. Wollesen

发明人： Yowjuang W. Liu ,  Donald L. Wollesen

IPC分类号： H01L214763

CPC分类号： H01L29/78 ,  H01L29/4933 ,  H01L29/66621

摘要： A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further includes a source region a drain region and a channel region. The source and drain region are laterally separated by the trench in which the trenched polysilicon gate is formed and partially extend laterally beneath the bottom surface of the trench. The channel region is formed in the silicon substrate beneath the bottom surface of the trench. In one embodiment the top surface of the trenched polysilicon gate is substantially planar to the substrate surface. In another embodiment the top surface and a portion of the trenched polysilicon gate are disposed above the substrate surface.

摘要翻译： 金属氧化物半导体（MOS）晶体管和用于改进器件缩放的方法包括形成在半导体衬底内蚀刻的沟槽内的沟槽多晶硅栅极，并且还包括源极区域，漏极区域和沟道区域。 源极和漏极区域被形成沟槽的多晶硅栅极的沟槽横向分开，并且部分地在沟槽的底表面下方延伸。 沟槽区域形成在沟槽底面下方的硅衬底中。 在一个实施例中，沟槽多晶硅栅极的顶表面基本上平行于衬底表面。 在另一个实施例中，沟槽多晶硅栅极的顶表面和一部分设置在衬底表面上方。

公开(公告)号：US06285054B1

公开(公告)日：2001-09-04

申请号：US09052057

申请日：1998-03-30

申请人： Yowjuang W. Liu ,  Donald L. Wollesen

发明人： Yowjuang W. Liu ,  Donald L. Wollesen

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/7883

摘要： A device structure and method for a non-volatile semiconductor device comprises a trenched floating gate and a control gate and further includes a source region, a drain region, a channel region, and an inter-gate dielectric layer. The trenched floating gate is formed in a trench etched into the semiconductor substrate. The trenched floating gate has a top surface which is substantially planar with a top surface of the substrate. The source and drain have a depth approximately equal to or greater than the depth of the trench and partially extend laterally underneath the bottom of the trench. The inter-gate dielectric layer is formed on the top surface of the trenched floating gate, and the control gate is formed on the inter-gate dielectric layer. In one embodiment, the device structure also includes sidewall dopings that are implanted regions formed in the semiconductor substrate which extend substantially vertically along the length of the trench. The sidewall dopings are immediately contiguous the vertical sides of the trench and laterally separate the trench from the source region and the drain region.

摘要翻译： 用于非易失性半导体器件的器件结构和方法包括沟槽浮置栅极和控制栅极，并且还包括源极区域，漏极区域，沟道区域和栅极间电介质层。 沟槽浮栅形成在蚀刻到半导体衬底中的沟槽中。 沟槽浮动栅极具有与衬底的顶表面基本平坦的顶表面。 源极和漏极的深度大约等于或大于沟槽的深度，并且部分地在沟槽的底部下方延伸。 栅极间电介质层形成在沟槽浮置栅极的顶表面上，并且控制栅极形成在栅极间电介质层上。 在一个实施例中，器件结构还包括侧壁掺杂，其是形成在半导体衬底中的注入区域，其沿沟槽的长度基本上垂直延伸。 侧壁掺杂物紧邻于沟槽的垂直侧面并且横向地将沟槽与源区域和漏极区域分开。

公开(公告)号：US06309919B1

公开(公告)日：2001-10-30

申请号：US09237001

申请日：1999-01-25

申请人： Yowjuang W. Liu ,  Donald L. Wollesen

发明人： Yowjuang W. Liu ,  Donald L. Wollesen

IPC分类号： H01L218238

CPC分类号： H01L29/7827 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78642

摘要： Complementary metal-oxide-semiconductor (CMOS) transistors (18,22) are formed with vertical channel regions (30,52) on an insulator substrate (14). Highly doped polysilicon gates (44,68) are formed in trenches (36,58) to extend laterally around the channel regions (30,52) as insulatively displaced therefrom by gate insulators (41,62) that are grown on the sidewalls of the trenches (36,58). The transistors (18,22), which are formed in respective mesas (20,24) have deeply implanted source regions (28,50) that are ohmically connected to the semiconductor surface via respective source connector regions (34,70).

摘要翻译： 互补金属氧化物半导体（CMOS）晶体管（18,22）在绝缘体衬底（14）上形成有垂直沟道区（30,52）。 高度掺杂多晶硅栅极（44,68）形成在沟槽（36,58）中，以通过栅极绝缘体（41,62）从沟槽区域（30,52）的侧壁上生长的绝缘体（41,62）绝缘地从沟槽区域（30,52）横向延伸， 沟槽（36,58）。 形成在相应的台面（20,24）中的晶体管（18,22）具有通过相应的源连接器区域（34,70）欧姆连接到半导体表面的深度注入的源极区域（28,50）。

公开(公告)号：US5864158A

公开(公告)日：1999-01-26

申请号：US832657

申请日：1997-04-04

申请人： Yowjuang W. Liu ,  Donald L. Wollesen

发明人： Yowjuang W. Liu ,  Donald L. Wollesen

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7827 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78642

摘要： Complementary metal-oxide-semiconductor (CMOS) transistors (18,22) are formed with vertical channel regions (30,52) on an insulator substrate (14). Highly doped polysilicon gates (44,68) are formed in trenches (36,58) to extend laterally around the channel regions (30,52) as insulatively displaced therefrom by gate insulators (41,62) that are grown on the sidewalls of the trenches (36,58). The transistors (18,22), which are formed in respective mesas (20,24) have deeply implanted source regions (28,50) that are ohmically connected to the semiconductor surface via respective source connector regions (34,70).

摘要翻译： 互补金属氧化物半导体（CMOS）晶体管（18,22）在绝缘体基板（14）上形成有垂直沟道区（30,52）。 高度掺杂多晶硅栅极（44,68）形成在沟槽（36,58）中，以通过在其上生长的栅极绝缘体（41,62）绝缘地从沟槽区域（30,52）横向延伸， 沟槽（36,58）。 形成在各个台面（20,24）中的晶体管（18,22）具有通过相应的源连接器区域（34,70）欧姆连接到半导体表面的深度注入的源极区域（28,50）。

公开(公告)号：US6147378A

公开(公告)日：2000-11-14

申请号：US52060

申请日：1998-03-30

申请人： Yowjuang W. Liu ,  Donald L. Wollesen

发明人： Yowjuang W. Liu ,  Donald L. Wollesen

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/788 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L29/66825 ,  H01L29/42336 ,  H01L29/7883 ,  Y10S257/905

摘要： A fully recessed device structure and method for low power applications comprises a trenched floating gate, a trenched control gate and a single wrap around buried drain region. The trenched floating gate and the trenched control gate are formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography. The fully recessed structure further comprises a buried source region, and a buried drain region that are each formed in the well junction region laterally separated by the trench. The upper boundaries of the buried source region and the buried drain region are of approximately the same depth as the top surface of the trenched floating gate. In one embodiment of the present invention the buried drain region has a lower boundary which partially extends laterally underneath the bottom surface of the trench to form a drain junction disposed along portions of the sidewall and bottom of the trench, and the buried source region has a lower boundary which is approximately less than the depth of the trench. In another embodiment of the present invention the buried source region has a lower boundary which partially extends laterally underneath the bottom surface of the trench to form a source junction disposed along portions of the sidewall and bottom of the trench, and the buried drain region has a lower boundary which is approximately less than the depth of the trench. In one embodiment of the present invention, sidewall dopings are formed in the substrate to shield the trenched control gate from the buried source and buried drain regions.

摘要翻译： 用于低功率应用的完全凹陷的器件结构和方法包括沟槽浮动栅极，沟槽控制栅极和围绕埋漏区的单个环绕。 沟槽浮置栅极和沟槽控制栅极形成在蚀刻到半导体衬底中的阱结区域中的单个沟槽中，以提供基本平坦的形貌。 完全凹陷结构还包括掩埋源区和埋入漏极区，每个掩埋漏极区形成在由沟槽横向隔开的阱结区域中。 掩埋源极区域和掩埋漏极区域的上边界与沟槽浮动栅极的顶表面的深度大致相同。 在本发明的一个实施例中，埋漏区具有下部边界，其部分地在沟槽底表面下方延伸，以形成沿着沟槽的侧壁和底部的一部分设置的漏极结，并且埋入源区具有 下边界大约小于沟槽的深度。 在本发明的另一个实施例中，掩埋源区具有下部边界，其部分地在沟槽的底表面下方延伸地形成沿着沟槽的侧壁和底部的部分设置的源极结，而漏极区域具有 下边界大约小于沟槽的深度。 在本发明的一个实施例中，在衬底中形成侧壁掺杂，以将沟槽的控制栅极与掩埋源和埋漏区区隔开。

公开(公告)号：US06225161B1

公开(公告)日：2001-05-01

申请号：US09470568

申请日：1999-12-22

申请人： Yowjuang W. Liu ,  Donald L. Wollesen

发明人： Yowjuang W. Liu ,  Donald L. Wollesen

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L29/42336 ,  H01L29/7883 ,  Y10S257/905

摘要： A fully recessed device structure and method for low power applications comprises a trenched floating gate, a trenched control gate and a single wrap around buried drain region. The trenched floating gate and the trenched control gate are formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography. The fully recessed structure further comprises a buried source region, and a buried drain region that are each formed in the well junction region laterally separated by the trench. The upper boundaries of the buried source region and the buried drain region are of approximately the same depth as the top surface of the trenched floating gate. In one embodiment of the present invention the buried drain region has a lower boundary which partially extends laterally underneath the bottom surface of the trench to form a drain junction disposed along portions of the sidewall and bottom of the trench, and the buried source region has a lower boundary which is approximately less than the depth of the trench. In another embodiment of the present invention the buried source region has a lower boundary which partially extends laterally underneath the bottom surface of the trench to form a source junction disposed along portions of the sidewall and bottom of the trench, and the buried drain region has a lower boundary which is approximately less than the depth of the trench. In one embodiment of the present invention, sidewall dopings are formed in the substrate to shield the trenched control gate from the buried source and buried drain regions.

摘要翻译： 用于低功率应用的完全凹陷的器件结构和方法包括沟槽浮动栅极，沟槽控制栅极和围绕埋漏区的单个环绕。 沟槽浮置栅极和沟槽控制栅极形成在蚀刻到半导体衬底中的阱结区域中的单个沟槽中，以提供基本平坦的形貌。 完全凹陷结构还包括掩埋源区和埋入漏极区，每个掩埋漏极区形成在由沟槽横向隔开的阱结区域中。 掩埋源极区域和掩埋漏极区域的上边界与沟槽浮动栅极的顶表面的深度大致相同。 在本发明的一个实施例中，埋漏区具有下部边界，其部分地在沟槽底表面下方延伸，以形成沿着沟槽的侧壁和底部的一部分设置的漏极结，并且埋入源区具有 下边界大约小于沟槽的深度。 在本发明的另一个实施例中，掩埋源区具有下部边界，其部分地在沟槽的底表面下方延伸地形成沿着沟槽的侧壁和底部的部分设置的源极结，而漏极区域具有 下边界大约小于沟槽的深度。 在本发明的一个实施例中，在衬底中形成侧壁掺杂，以将沟槽的控制栅极与掩埋源和埋漏区区隔开。

公开(公告)号：US6097061A

公开(公告)日：2000-08-01

申请号：US52051

申请日：1998-03-30

申请人： Yowjuang W. Liu ,  Donald L. Wollesen

发明人： Yowjuang W. Liu ,  Donald L. Wollesen

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/76 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L29/78 ,  H01L29/66621 ,  H01L29/4933

摘要： A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further includes a source region, a drain region, and a channel region. The source and drain region are laterally separated by the trench in which the trenched polysilicon gate is formed and partially extend laterally beneath the bottom surface of the trench. The channel region is formed in the silicon substrate beneath the bottom surface of the trench. In one embodiment, the top surface of the trenched polysilicon gate is substantially planar to the substrate surface. In another embodiment, the top surface and a portion of the trenched polysilicon gate are disposed above the substrate surface.

摘要翻译： 金属氧化物半导体（MOS）晶体管和用于改进器件缩放的方法包括形成在半导体衬底内蚀刻的沟槽内的沟槽多晶硅栅极，还包括源极区，漏极区和沟道区。 源极和漏极区域被形成沟槽的多晶硅栅极的沟槽横向分开，并且部分地在沟槽的底表面下方延伸。 沟槽区域形成在沟槽底面下方的硅衬底中。 在一个实施例中，沟槽多晶硅栅极的顶表面基本上平行于衬底表面。 在另一个实施例中，沟槽多晶硅栅极的顶表面和一部分设置在衬底表面上方。

公开(公告)号：US5990515A

公开(公告)日：1999-11-23

申请号：US52062

申请日：1998-03-30

申请人： Yowjuang W. Liu ,  Donald L. Wollesen

发明人： Yowjuang W. Liu ,  Donald L. Wollesen

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/72

CPC分类号： H01L29/66825 ,  H01L29/42336

摘要： A non-volatile semiconductor cell structure and method comprises a trenched floating gate, a sidewall doping and a corner doping and further includes a sidewall doped region, a corner doped region, a channel region, and an inter-gate dielectric layer, and a control gate. The trenched floating gate is formed in a trench etched into the semiconductor substrate. In a preferred embodiment, the trenched floating gate has a top surface which is substantially planar with a top surface of the semiconductor substrate. The control gate and the inter-gate dielectric are formed on the top surface of the trenched floating gate. The sidewall doped region and the corner doped region are laterally separated by the trench in which the trenched floating gate is formed. The sidewall doped region has a depth which is greater than the depth of the trench, and the corner doped region has a depth which is less than the depth of the trench. The sidewall doping is a diffusion region formed in the sidewall doped region of the semiconductor substrate and is immediately contiguous to a vertical sidewall of the trench and immediately contiguous to the substrate surface. The corner doping is a diffusion region formed in the corner doped region of the semiconductor substrate and is immediately contiguous the upper vertical sidewall of the trench which is opposite the vertical sidewall along which the sidewall doping is formed and is immediately contiguous the substrate surface.

摘要翻译： 非挥发性半导体单元结构和方法包括沟槽浮置栅极，侧壁掺杂和角掺杂，并且还包括侧壁掺杂区域，角掺杂区域，沟道区域和栅极间介电层，以及控制 门。 沟槽浮栅形成在蚀刻到半导体衬底中的沟槽中。 在优选实施例中，沟槽浮动栅极具有与半导体衬底的顶表面基本平坦的顶表面。 控制栅极和栅极间电介质形成在沟槽浮动栅极的顶表面上。 侧壁掺杂区域和拐角掺杂区域被形成有沟槽浮动栅极的沟槽横向分开。 所述侧壁掺杂区域的深度大于所述沟槽的深度，并且所述拐角掺杂区域的深度小于所述沟槽的深度。 侧壁掺杂是形成在半导体衬底的侧壁掺杂区域中的扩散区域，并且紧邻于沟槽的垂直侧壁并且紧邻衬底表面。 角掺杂是形成在半导体衬底的角掺杂区域中的扩散区域，并且立即与沟槽的上垂直侧壁邻接，该垂直侧壁与形成侧壁掺杂的垂直侧壁相对，并且立即与衬底表面相邻。

公开(公告)号：US06764904B1

公开(公告)日：2004-07-20

申请号：US09629780

申请日：2000-07-31

申请人： Yowjuang W. Liu ,  Donald L. Wollesen

发明人： Yowjuang W. Liu ,  Donald L. Wollesen

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/7883

摘要： A device structure and method for a non-volatile semiconductor device comprises a trenched floating gate and a control gate and further includes a source region, a drain region, a channel region, and an inter-gate dielectric layer. The trenched floating gate is formed in a trench etched into the semiconductor substrate. The trenched floating gate has a top surface which is substantially planar with a top surface of the substrate. The source and drain region have a depth approximately equal to or greater than the depth of the trench and partially extend laterally underneath the bottom of the trench. The inter-gate dielectric layer is formed on the top surface of the trenched floating gate, and the control gate is formed on the inter-gate dielectric layer. In one embodiment, the device structure also includes sidewall dopings that are implanted regions formed in the semiconductor substrate which extend substantially vertically along the length of the trench. The sidewall dopings are immediately contiguous the vertical sides of the trench and laterally separate the trench from the source region and the drain region.

摘要翻译： 用于非易失性半导体器件的器件结构和方法包括沟槽浮置栅极和控制栅极，并且还包括源极区域，漏极区域，沟道区域和栅极间电介质层。 沟槽浮栅形成在蚀刻到半导体衬底中的沟槽中。 沟槽浮动栅极具有与衬底的顶表面基本平坦的顶表面。 源极和漏极区域的深度大约等于或大于沟槽的深度，并且部分地在沟槽的底部下方延伸。 栅极间电介质层形成在沟槽浮置栅极的顶表面上，并且控制栅极形成在栅极间电介质层上。 在一个实施例中，器件结构还包括侧壁掺杂，其是形成在半导体衬底中的注入区域，其沿沟槽的长度基本上垂直延伸。 侧壁掺杂物紧邻于沟槽的垂直侧面并且横向地将沟槽与源区域和漏极区域分开。