公开(公告)号：US5972773A

公开(公告)日：1999-10-26

申请号：US869466

申请日：1997-06-05

申请人： Yowjuang W. Liu ,  Ming-Ren Lin

发明人： Yowjuang W. Liu ,  Ming-Ren Lin

IPC分类号： H01L21/32 ,  H01L21/762

CPC分类号： H01L21/76205 ,  H01L21/32

摘要： A novel semiconductor fabrication process having the advantages of conventional LOCOS (process simplicity and reduced defects) while providing a scaleable, planar isolation region between active regions formed in a semiconductor substrate. The preferred process includes formation of a barrier layer and a masking layer over the substrate. An active region mask defines an exposure region of the masking layer. The exposure region is etched to form an opening, exposing a portion of barrier layer in the opening. A spacer is added inside the opening, around a perimeter of the opening to define a second exposure region. The barrier layer, and substrate, under the second exposure region, but not under the spacer, are etched to form an isolation region opening. The isolation region opening may have a suitable isolating material, such as silicon oxide, grown, filled, or some combination of both, in the isolation region opening. The spacer width and the depth of the isolation region opening are independently controllable.

摘要翻译： 一种新颖的半导体制造方法，其具有常规LOCOS（工艺简单性和降低的缺陷）的优点，同时在半导体衬底中形成的有源区域之间提供可扩展的平面隔离区域。 优选的方法包括在衬底上形成阻挡层和掩模层。 有源区掩模限定掩模层的曝光区域。 蚀刻曝光区域以形成开口，暴露开口中的阻挡层的一部分。 在开口内部，围绕开口的周边添加间隔物，以限定第二曝光区域。 在第二曝光区域下方但不在间隔物下方的阻挡层和衬底被蚀刻以形成隔离区域开口。 在隔离区开口中，隔离区开口可以具有合适的隔离材料，例如氧化硅，生长，填充或两者的某种组合。 间隔物宽度和隔离区域开口的深度是独立可控的。

公开(公告)号：US06373103B1

公开(公告)日：2002-04-16

申请号：US09541124

申请日：2000-03-31

申请人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

发明人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

IPC分类号： H01L2701

CPC分类号： H01L29/78624 ,  H01L29/41733 ,  H01L29/78612

摘要： A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

摘要翻译： 半导体器件包括具有源极，主体和漏极区域的半导体层的晶片。 半导体区域的导电区域与源极区域和体区域重叠并电耦合。 源极和体区的电耦合减少了半导体器件中的浮体效应。 构造半导体器件的方法利用间隔物，掩模和/或倾斜注入来形成与半导体层的源极和体区域重叠的源极体导电区域，以及位于半导体器件的内部的漏极导电区域 漏极区域。

公开(公告)号：US06275972B1

公开(公告)日：2001-08-14

申请号：US09310806

申请日：1999-05-12

申请人： Wei Long ,  Yowjuang W. Liu

发明人： Wei Long ,  Yowjuang W. Liu

IPC分类号： G06F1750

CPC分类号： H01L22/12 ,  G01R31/2621

摘要： A method for extracting a channel length between a source and a drain in a substrate of a transistor is disclosed herein. The method includes forward biasing the source with respect to the substrate to inject a charge into the substrate, collecting the charge at the drain, and calculating the channel length from the charge collected at the drain.

摘要翻译： 本文公开了一种在晶体管的衬底中提取源极和漏极之间的沟道长度的方法。 该方法包括相对于衬底向源偏置源，以将电荷注入到衬底中，在漏极处收集电荷，以及从在漏极处收集的电荷计算沟道长度。

公开(公告)号：US06232632B1

公开(公告)日：2001-05-15

申请号：US09436503

申请日：1999-11-09

申请人： Yowjuang W. Liu

发明人： Yowjuang W. Liu

IPC分类号： H01L29788

CPC分类号： H01L27/11553 ,  H01L27/115

摘要： Double density non-volatile memory cells having a trench structure are formed in a substrate, thereby facilitating miniaturization, improved planarization and low power programming and erasing. Each double density cell comprises two floating gates and a common control gate. Each pair of double density cells shares a common source region. Embodiments include forming first and second trenches in a substrate and depositing a tunnel dielectric layer in each trench. Polycrystalline silicon is then deposited filling each trench and a hole is etched forming two floating gate electrodes in each trench. An interpoly dielectric layer is then formed and a substantially T-shaped control gate electrode is deposited filling the hole between the floating gates and extending on the substrate.

摘要翻译： 在衬底中形成具有沟槽结构的双重密度非易失性存储单元，从而便于小型化，改进的平面化和低功率编程和擦除。 每个双密度单元包括两个浮动栅极和公共控制栅极。 每对双密度细胞共享一个共同的源区。 实施例包括在衬底中形成第一和第二沟槽，并在每个沟槽中沉积隧道介电层。 然后沉积多晶硅填充每个沟槽，并且蚀刻孔，在每个沟槽中形成两个浮置栅电极。 然后形成间隔电介质层，并且沉积基本上T形的控制栅极，填充浮置栅极之间的孔并在衬底上延伸。

公开(公告)号：US06184105B2

公开(公告)日：2001-02-06

申请号：US08861553

申请日：1997-05-22

申请人： Yowjuang W. Liu ,  Sunil D. Mehta

发明人： Yowjuang W. Liu ,  Sunil D. Mehta

IPC分类号： H01L2176

CPC分类号： H01L21/76235 ,  H01L21/76202 ,  H01L29/0649

摘要： A method of fabricating integrated circuit including field effect transistors (FET) having source and drain regions and a gate and with LOCOS isolation by selectively forming, after the FETs are fabricated, trench openings in the source or drain regions or in the LOCOS isolation to maximize the isolation in selected areas while reducing the amount of silicon used by the isolation.

摘要翻译： 一种制造集成电路的方法，其包括具有源极和漏极区域以及栅极和FETOS隔离的场效应晶体管（FET），其通过在FET被制造之后通过选择性地形成在源极或漏极区域中或在LOCOS隔离中的最大化 在选择的区域进行隔离，同时减少隔离使用的硅的量。

公开(公告)号：US6147378A

公开(公告)日：2000-11-14

申请号：US52060

申请日：1998-03-30

申请人： Yowjuang W. Liu ,  Donald L. Wollesen

发明人： Yowjuang W. Liu ,  Donald L. Wollesen

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/788 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L29/66825 ,  H01L29/42336 ,  H01L29/7883 ,  Y10S257/905

摘要： A fully recessed device structure and method for low power applications comprises a trenched floating gate, a trenched control gate and a single wrap around buried drain region. The trenched floating gate and the trenched control gate are formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography. The fully recessed structure further comprises a buried source region, and a buried drain region that are each formed in the well junction region laterally separated by the trench. The upper boundaries of the buried source region and the buried drain region are of approximately the same depth as the top surface of the trenched floating gate. In one embodiment of the present invention the buried drain region has a lower boundary which partially extends laterally underneath the bottom surface of the trench to form a drain junction disposed along portions of the sidewall and bottom of the trench, and the buried source region has a lower boundary which is approximately less than the depth of the trench. In another embodiment of the present invention the buried source region has a lower boundary which partially extends laterally underneath the bottom surface of the trench to form a source junction disposed along portions of the sidewall and bottom of the trench, and the buried drain region has a lower boundary which is approximately less than the depth of the trench. In one embodiment of the present invention, sidewall dopings are formed in the substrate to shield the trenched control gate from the buried source and buried drain regions.

摘要翻译： 用于低功率应用的完全凹陷的器件结构和方法包括沟槽浮动栅极，沟槽控制栅极和围绕埋漏区的单个环绕。 沟槽浮置栅极和沟槽控制栅极形成在蚀刻到半导体衬底中的阱结区域中的单个沟槽中，以提供基本平坦的形貌。 完全凹陷结构还包括掩埋源区和埋入漏极区，每个掩埋漏极区形成在由沟槽横向隔开的阱结区域中。 掩埋源极区域和掩埋漏极区域的上边界与沟槽浮动栅极的顶表面的深度大致相同。 在本发明的一个实施例中，埋漏区具有下部边界，其部分地在沟槽底表面下方延伸，以形成沿着沟槽的侧壁和底部的一部分设置的漏极结，并且埋入源区具有 下边界大约小于沟槽的深度。 在本发明的另一个实施例中，掩埋源区具有下部边界，其部分地在沟槽的底表面下方延伸地形成沿着沟槽的侧壁和底部的部分设置的源极结，而漏极区域具有 下边界大约小于沟槽的深度。 在本发明的一个实施例中，在衬底中形成侧壁掺杂，以将沟槽的控制栅极与掩埋源和埋漏区区隔开。

公开(公告)号：US6107667A

公开(公告)日：2000-08-22

申请号：US151146

申请日：1998-09-10

申请人： Judy Xilin An ,  Bin Yu ,  Yowjuang W. Liu

发明人： Judy Xilin An ,  Bin Yu ,  Yowjuang W. Liu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76 ,  H01L27/088 ,  H01L27/095 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L21/28194 ,  H01L21/28123 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S257/90

摘要： A method for making a ULSI MOSFET includes establishing a void in a field oxide layer on a silicon substrate and filling the center of the void with a gate electrode. A high-k gate insulator is sandwiched between the gate electrode and the substrate. Around the void, a low-k gate spacer is formed, with the gate spacer being disposed directly above the source and drain extensions of the MOSFET.

摘要翻译： 制造ULSI MOSFET的方法包括在硅衬底上的场氧化物层中建立空隙并用栅电极填充空隙的中心。 高k栅极绝缘体夹在栅电极和衬底之间。 围绕空隙，形成低k栅极间隔物，栅极间隔物直接设置在MOSFET的源极和漏极延伸部分的上方。

公开(公告)号：US6069485A

公开(公告)日：2000-05-30

申请号：US237539

申请日：1999-01-26

申请人： Wei Long ,  Yowjuang W. Liu ,  Chun Jiang

发明人： Wei Long ,  Yowjuang W. Liu ,  Chun Jiang

IPC分类号： G01N27/22 ,  H01L21/66 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/1045 ,  G01N27/221 ,  H01L22/14

摘要： A method and apparatus that uses gate-to-substrate capacitance with varying amounts of source/drain junction bias to measure channel lateral doping profile by applying a series of different voltages between the source/drain and the substrate. The gate capacitance is measured for the different voltages. The capacitance is used to calculate the depletion width. From the depletion width, channel doping is calculated. Using this method direct evidence of a localized Boron pile up at source/drain edge is shown.

摘要翻译： 一种使用具有不同量的源极/漏极结偏置的栅极至衬底电容以通过在源极/漏极和衬底之间施加一系列不同电压来测量沟道横向掺杂分布的方法和装置。 对不同的电压测量栅极电容。 电容用于计算耗尽宽度。 从耗尽宽度，计算通道掺杂。 使用这种方法显示了在源极/漏极边缘处的局部硼堆积的直接证据。

公开(公告)号：US06040597A

公开(公告)日：2000-03-21

申请号：US23166

申请日：1998-02-13

申请人： Unsoon Kim ,  Yowjuang W. Liu ,  Yu Sun

发明人： Unsoon Kim ,  Yowjuang W. Liu ,  Yu Sun

IPC分类号： H01L21/762 ,  H01L29/788

CPC分类号： H01L21/76232 ,  H01L21/76237

摘要： A wet etching process for establishing isolation grooves in a flash memory core wafer includes depositing nitride and/or oxide layers on a silicon substrate of the wafer, depositing a photoresist layer thereon, and then exposing predetermined portions of the photoresist layer to ultraviolet light to establish a desired groove pattern in the photoresist layer. A dry etching process is then used to remove the nitride and/or oxide layers beneath the groove pattern of the photoresist layer to thereby expose portions of the substrate. Next, the wafer is disposed in a wet etching solution such as potassium hydroxide to form grooves in the exposed portions of the silicon substrate. The wafer is oriented and disposed in the bath as appropriate for forming V-shaped grooves, such that after etching, the angled walls of the grooves can be easily exposed to a dopant beam directly above the wafer, without having to tilt the wafer or beam source. Thereby, the walls of the grooves are easily implanted with dopant.

摘要翻译： 用于在闪速存储器芯晶片中建立隔离槽的湿蚀刻工艺包括在晶片的硅衬底上沉积氮化物和/或氧化物层，在其上沉积光致抗蚀剂层，然后将光致抗蚀剂层的预定部分暴露于紫外光以建立 在光致抗蚀剂层中的期望的凹槽图案。 然后使用干蚀刻工艺去除光致抗蚀剂层的凹槽图案下方的氮化物和/或氧化物层，从而暴露衬底的部分。 接下来，将晶片设置在诸如氢氧化钾的湿蚀刻溶液中，以在硅衬底的暴露部分中形成凹槽。 晶片被定向并适当地设置在浴中以形成V形槽，使得在蚀刻之后，槽的成角度的壁可以容易地暴露于直接在晶片上方的掺杂剂束，而不必使晶片或光束倾斜 资源。 因此，槽的壁容易用掺杂剂注入。

公开(公告)号：US5945705A

公开(公告)日：1999-08-31

申请号：US510118

申请日：1995-08-01

申请人： Yowjuang W. Liu ,  Sameer S. Haddad

发明人： Yowjuang W. Liu ,  Sameer S. Haddad

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L29/7885

摘要： A strip of a semiconductor material (for example, P type silicon) is oxidized and the resulting strip of oxide is removed leaving a depression in the upper surface of the semiconductor material which has steep sidewalls. The steep sidewalls do not have significant ion impact damage because they are formed by oxidation and not by reactive ion etching of the semiconductor material. A high quality tunnel oxide can therefore be grown on the steep sidewalls. Floating gates are then formed on the tunnel oxide, corresponding word lines are formed over the floating gates, a conductive region (for example, N type silicon) is formed into the bottom of the depression, and a number of conductive regions (for example, N type silicon) corresponding with the floating gates are formed above the rim of the depression. The resulting bit transistors have channel regions which extend in a vertical dimension under floating gates along the surface of the sidewall. Because the depth and profile of the depression is determined primarily by oxidation and not by lithography, very small geometry bit transistors can be made.