摘要:
The present invention generally relates to simulating a lithographic process, and more particularly to methods for smart selection and smart weighting when selecting parameters and/or kernels used in aerial image computation. According to one aspect, advantages in simulation throughput and/or accuracy can be achieved by selecting TCC kernels more intelligently, allowing highly accurate aerial images to be simulated using a relatively fewer number of TCC kernels than in the state of the art. In other words, the present invention allows for aerial images to be simulated with the same or better accuracy using much less simulation throughput than required in the prior art, all else being equal.
摘要:
The present invention generally relates to simulating a lithographic process, and more particularly to methods for smart selection and smart weighting when selecting parameters and/or kernels used in aerial image computation. According to one aspect, advantages in simulation throughput and/or accuracy can be achieved by selecting TCC kernels more intelligently, allowing highly accurate aerial images to be simulated using a relatively fewer number of TCC kernels than in the state of the art. In other words, the present invention allows for aerial images to be simulated with the same or better accuracy using much less simulation throughput than required in the prior art, all else being equal.
摘要:
The present invention generally relates to simulating a lithographic process, and more particularly to methods for smart selection and smart weighting when selecting parameters and/or kernels used in aerial image computation. According to one aspect, advantages in simulation throughput and/or accuracy can be achieved by selecting TCC kernels more intelligently, allowing highly accurate aerial images to be simulated using a relatively fewer number of TCC kernels than in the state of the art. In other words, the present invention allows for aerial images to be simulated with the same or better accuracy using much less simulation throughput than required in the prior art, all else being equal.
摘要:
Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created.
摘要:
Systems and methods for tuning photolithographic processes are described. A model of a target scanner is maintained defining sensitivity of the target scanner with reference to a set of tunable parameters. A differential model represents deviations of the target scanner from the reference. The target scanner may be tuned based on the settings of the reference scanner and the differential model. Performance of a family of related scanners may be characterized relative to the performance of a reference scanner. Differential models may include information such as parametric offsets and other differences that may be used to simulate the difference in imaging behavior.
摘要:
A method for determining an image of a mask pattern in a resist coated on a substrate, the method including determining an aerial image of the mask pattern at substrate level; and convolving the aerial image with at least two orthogonal convolution kernels to determine a resist image that is representative of the mask pattern in the resist.
摘要:
A method for determining an image of a mask pattern in a resist coated on a substrate, the method including determining an aerial image of the mask pattern at substrate level; and convolving the aerial image with at least two orthogonal convolution kernels to determine a resist image that is representative of the mask pattern in the resist.
摘要:
Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created.
摘要:
The present invention relates generally to methods and apparatuses for test pattern selection for computational lithography model calibration. According to some aspects, the pattern selection algorithms of the present invention can be applied to any existing pool of candidate test patterns. According to some aspects, the present invention automatically selects those test patterns that are most effective in determining the optimal model parameter values from an existing pool of candidate test patterns, as opposed to designing optimal patterns. According to additional aspects, the selected set of test patterns according to the invention is able to excite all the known physics and chemistry in the model formulation, making sure that the wafer data for the test patterns can drive the model calibration to the optimal parameter values that realize the upper bound of prediction accuracy imposed by the model formulation.
摘要:
A method for determining a difference between a reference image and a further image of a pattern, the method including determining a reference imaging function; determining parameters of a difference function representative of a difference between the reference imaging function and a further imaging function; calculating a difference between the reference image and the further image of the pattern based on the difference function and the determined parameters.