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    ANALOG-TO-DIGITAL CONVERTER AND DEVICES INCLUDING THE SAME
    4.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER AND DEVICES INCLUDING THE SAME 有权
    模拟数字转换器和包括其的器件

    公开(公告)号：US20110292261A1

    公开(公告)日：2011-12-01

    申请号：US13116551

    申请日：2011-05-26

    申请人： CHI HO HWANG ,  Yu Jin Park ,  Yong Lim ,  Han Yang

    发明人： CHI HO HWANG ,  Yu Jin Park ,  Yong Lim ,  Han Yang

    IPC分类号： H04N5/335 ,  H03M1/12

    CPC分类号： H04N5/374 ,  H03M1/123 ,  H03M1/14 ,  H03M1/56 ,  H03M1/765 ,  H04N5/3575 ,  H04N5/378

    摘要： An analog-to-digital converter including a comparator configured to compare a pixel signal received at a first input terminal of the comparator with a ramp signal received at a second input terminal of the comparator and generate a comparison signal as a result of the comparison; and a ramp signal supply circuit configured to provide the ramp signal to the comparator, wherein the ramp signal supply circuit generates a first signal as part of the ramp signal in response to the comparison signal and a first clock signal being received at the ramp signal supply circuit, wherein a slope of the first signal sequentially changes until the comparison signal makes a transition from one logic level to another and, after the transition, the ramp signal supply circuit generates a second signal as part of the ramp signal, wherein a slope of the second signal sequentially changes, wherein the slope of the second signal is opposite the slope of the first signal.

    摘要翻译： 一种模数转换器，包括：比较器，被配置为将比较器的第一输入端接收的像素信号与比较器的第二输入端接收的斜坡信号进行比较，并作为比较结果生成比较信号; 以及斜坡信号供给电路，被配置为向所述比较器提供所述斜坡信号，其中所述斜坡信号供给电路响应于所述比较信号而产生作为所述斜坡信号的一部分的第一信号，以及在所述斜坡信号供给处接收到的第一时钟信号 电路，其中所述第一信号的斜率顺序地改变，直到所述比较信号从一个逻辑电平转换到另一个逻辑电平，并且在所述转换之后，所述斜坡信号供应电路产生作为所述斜坡信号的一部分的第二信号，其中， 第二信号依次变化，其中第二信号的斜率与第一信号的斜率相反。

    Analog-to-digital converter and devices including the same
    5.
    发明授权
    Analog-to-digital converter and devices including the same 有权
    模数转换器和包括其的器件

    公开(公告)号：US08482447B2

    公开(公告)日：2013-07-09

    申请号：US13116551

    申请日：2011-05-26

    申请人： Chi Ho Hwang ,  Yu Jin Park ,  Yong Lim ,  Han Yang

    发明人： Chi Ho Hwang ,  Yu Jin Park ,  Yong Lim ,  Han Yang

    IPC分类号： H03M1/56

    CPC分类号： H04N5/374 ,  H03M1/123 ,  H03M1/14 ,  H03M1/56 ,  H03M1/765 ,  H04N5/3575 ,  H04N5/378

    摘要： An analog-to-digital converter including a comparator configured to compare a pixel signal received at a first input terminal of the comparator with a ramp signal received at a second input terminal of the comparator and generate a comparison signal as a result of the comparison; and a ramp signal supply circuit configured to provide the ramp signal to the comparator, wherein the ramp signal supply circuit generates a first signal as part of the ramp signal in response to the comparison signal and a first clock signal being received at the ramp signal supply circuit, wherein a slope of the first signal sequentially changes until the comparison signal makes a transition from one logic level to another and, after the transition, the ramp signal supply circuit generates a second signal as part of the ramp signal, wherein a slope of the second signal sequentially changes, wherein the slope of the second signal is opposite the slope of the first signal.

    摘要翻译： 一种模数转换器，包括：比较器，被配置为将比较器的第一输入端接收的像素信号与比较器的第二输入端接收的斜坡信号进行比较，并作为比较结果生成比较信号; 以及斜坡信号供给电路，被配置为向所述比较器提供所述斜坡信号，其中所述斜坡信号供给电路响应于所述比较信号而产生作为所述斜坡信号的一部分的第一信号，以及在所述斜坡信号供给处接收到的第一时钟信号 电路，其中所述第一信号的斜率顺序地改变，直到所述比较信号从一个逻辑电平转换到另一个逻辑电平，并且在所述转换之后，所述斜坡信号供应电路产生作为所述斜坡信号的一部分的第二信号，其中， 第二信号依次变化，其中第二信号的斜率与第一信号的斜率相反。

    Flash Memory Device With an Array of Gate Columns Penetrating Through a Cell Stack
    6.
    发明申请
    Flash Memory Device With an Array of Gate Columns Penetrating Through a Cell Stack 有权
    闪存器件具有通过单元堆栈穿透的栅极列阵列

    公开(公告)号：US20120217572A1

    公开(公告)日：2012-08-30

    申请号：US13469206

    申请日：2012-05-11

    申请人： Hack Seob Shin ,  Kyoung Hwan Park ,  Young Ok Hong ,  Yu Jin Park

    发明人： Hack Seob Shin ,  Kyoung Hwan Park ,  Young Ok Hong ,  Yu Jin Park

    IPC分类号： H01L29/792

    CPC分类号： G11C16/0483 ,  G11C5/02 ,  H01L27/0688 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582

    摘要： A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.

    摘要翻译： 闪存器件包括衬底; 具有用于提供结区域和沟道区域的半导体层和用于绝缘半导体层的层间隔离层的电池堆，其中半导体层和层间隔离层被重复堆叠; 门列的阵列，栅极柱穿过电池堆，垂直于衬底; 以及引入到栅极列和电池堆之间的接口中的陷阱层叠堆积以存储电荷。

    Manufacturing method of flash memory device comprising gate columns penetrating through a cell stack
    7.
    发明授权
    Manufacturing method of flash memory device comprising gate columns penetrating through a cell stack 有权
    闪存器件的制造方法包括穿过单元堆叠的栅极列

    公开(公告)号：US07867831B2

    公开(公告)日：2011-01-11

    申请号：US12212819

    申请日：2008-09-18

    申请人： Hack Seob Shin ,  Kyoung Hwan Park ,  Young Ok Hong ,  Yu Jin Park

    发明人： Hack Seob Shin ,  Kyoung Hwan Park ,  Young Ok Hong ,  Yu Jin Park

    IPC分类号： H01L21/82

    CPC分类号： G11C16/0483 ,  G11C5/02 ,  H01L27/0688 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582

    摘要： A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked. The flash memory device further includes an array of gate columns penetrating through the cell stack, perpendicular to the substrate and cutting through the junction areas to dispose the junction areas at both sides thereof, and a trap layered stack introduced into an interface between the gate column and the cell stack to store charge.

    摘要翻译： 闪速存储器件包括衬底，具有半导体层的电池堆，其中用于将区域之间设置到沟道区域的结区域形成为条状，以及用于绝缘半导体层的层间隔离层，其中半导体 层和层间隔离层重复堆叠。 闪存器件还包括穿过电池堆的栅极阵列阵列，垂直于衬底并切割穿过接合区域以在其两侧布置接合区域，以及陷阱层叠堆叠引入到栅极柱 和电池堆来存储电荷。

    Flash Memory Device and Method for Manufacturing the Same
    8.
    发明申请
    Flash Memory Device and Method for Manufacturing the Same 有权
    闪存设备及其制造方法

    公开(公告)号：US20090296476A1

    公开(公告)日：2009-12-03

    申请号：US12212819

    申请日：2008-09-18

    申请人： Hack Seob Shin ,  Kyoung Hwan Park ,  Young Ok Hong ,  Yu Jin Park

    发明人： Hack Seob Shin ,  Kyoung Hwan Park ,  Young Ok Hong ,  Yu Jin Park

    IPC分类号： G11C11/34 ,  H01L21/00

    CPC分类号： G11C16/0483 ,  G11C5/02 ,  H01L27/0688 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582

    摘要： A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked. The flash memory device further includes an array of gate columns penetrating through the cell stack, perpendicular to the substrate and cutting through the junction areas to dispose the junction areas at both sides thereof, and a trap layered stack introduced into an interface between the gate column and the cell stack to store charge.

    摘要翻译： 闪速存储器件包括衬底，具有半导体层的电池堆，其中用于将区域之间设置到沟道区域的结区域形成为条状，以及用于绝缘半导体层的层间隔离层，其中半导体 层和层间隔离层重复堆叠。 闪存器件还包括穿过电池堆的栅极阵列阵列，垂直于衬底并切割穿过接合区域以在其两侧布置接合区域，以及陷阱层叠堆叠引入到栅极柱 和电池堆来存储电荷。

    Flash Memory Device With an Array of Gate Columns Penetrating Through a Cell Stack
    10.
    发明申请
    Flash Memory Device With an Array of Gate Columns Penetrating Through a Cell Stack 有权
    闪存器件具有通过单元堆栈穿透的栅极列阵列

    公开(公告)号：US20100308398A1

    公开(公告)日：2010-12-09

    申请号：US12857678

    申请日：2010-08-17

    申请人： Hack Seob Shin ,  Kyoung Hwan Park ,  Young Ok Hong ,  Yu Jin Park

    发明人： Hack Seob Shin ,  Kyoung Hwan Park ,  Young Ok Hong ,  Yu Jin Park

    IPC分类号： H01L29/792

    CPC分类号： G11C16/0483 ,  G11C5/02 ,  H01L27/0688 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582

    摘要： A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.

    摘要翻译： 闪存器件包括衬底; 具有用于提供结区域和沟道区域的半导体层和用于绝缘半导体层的层间隔离层的电池堆，其中半导体层和层间隔离层被重复堆叠; 门列的阵列，栅极柱穿过电池堆，垂直于衬底; 以及引入到栅极列和电池堆之间的接口中的陷阱层叠堆积以存储电荷。