公开(公告)号：US06630384B1

公开(公告)日：2003-10-07

申请号：US09971483

申请日：2001-10-05

申请人： Yu Sun ,  Michael A. Van Buskirk ,  Mark T. Ramsbey

发明人： Yu Sun ,  Michael A. Van Buskirk ,  Mark T. Ramsbey

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming a first set of memory cell gates over the charge trapping dielectric in the core region; forming a conformal insulation material layer around the first set of memory cell gates; and forming a second set of memory cell gates in the core region, wherein each memory cell gate of the second set of memory cell gates is adjacent to at least one memory cell gate of the first set of memory cell gates, each memory cell gate of the first set of memory cell gates is adjacent at least one memory cell gate of the second set of memory cell gates, and the conformal insulation material layer is positioned between each adjacent memory cell gate.

摘要翻译： 本发明的一个方面涉及一种形成非易失性半导体存储器件的方法，包括在衬底上形成电荷俘获电介质，所述衬底具有芯区域和外围区域; 在芯区域中的电荷俘获电介质上形成第一组存储单元栅极; 在所述第一组存储单元栅极周围形成保形绝缘材料层; 以及在所述核心区域中形成第二组存储器单元栅极，其中所述第二组存储单元栅极的每个存储单元栅极与所述第一组存储单元栅极的至少一个存储单元栅极相邻， 第一组存储单元栅极与第二组存储单元栅极的至少一个存储单元栅极相邻，并且保形绝缘材料层位于每个相邻的存储单元栅极之间。

公开(公告)号：US06529412B1

公开(公告)日：2003-03-04

申请号：US10050257

申请日：2002-01-16

申请人： Pau-Ling Chen ,  Michael A. Van Buskirk ,  Yu Sun

发明人： Pau-Ling Chen ,  Michael A. Van Buskirk ,  Yu Sun

IPC分类号： G11C1600

CPC分类号： G11C16/28 ,  G11C16/0491

摘要： A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line precharge and hold circuit which is operable to apply and maintain a source terminal voltage (e.g., about 0 volts, ground) to a bit line associated with the source terminal of a cell adjacent to the cell which is sensed during a read operation, wherein the applied source terminal voltage is substantially the same as the bit line virtual ground voltage applied to the source terminal bit line of the selected memory cell to be sensed. The system also includes a drain bit line circuit operable to generate a drain terminal voltage for a drain terminal of a selected memory cell to be sensed. The system further includes a selective bit line decode circuit which is operable to select the bit lines of a memory cell to be sensed and the bit line of an adjacent cell, and a core cell sensing circuit which is operable to sense a core cell sense current at a bit line associated with a source terminal of the selected memory cell to be sensed during memory read operations, and produce an indication of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.

摘要翻译： 公开了一种用于产生用于虚拟接地闪速存储器操作的闪存单元的逻辑状态的指示的系统。 该系统包括位线预充电和保持电路，其可操作以将源极端子电压（例如，约0伏，接地）施加并保持到与该单元相邻的单元的源极端子相关联的位线 读取操作，其中所施加的源极端子电压与施加到要被感测的所选存储器单元的源极端子位线的位线虚拟接地电压基本相同。 该系统还包括漏极位线电路，其可操作以产生用于待感测的选定存储单元的漏极端子的漏极端子电压。 该系统还包括选择性位线解码电路，其可操作以选择要感测的存储器单元的位线和相邻单元的位线;以及核心单元感测电路，其可操作以感测核心单元感测电流 在与存储器读取操作期间被感测的所选存储器单元的源极端子相关联的位线处，并且产生闪存单元逻辑状态的指示，其基本上与相邻单元的电荷共享泄漏电流无关。

公开(公告)号：US06730564B1

公开(公告)日：2004-05-04

申请号：US10217821

申请日：2002-08-12

申请人： Mark T. Ramsbey ,  Yu Sun ,  Chi Chang ,  Hidehiko Shiraiwa

发明人： Mark T. Ramsbey ,  Yu Sun ,  Chi Chang ,  Hidehiko Shiraiwa

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534 ,  Y10S438/954

摘要： The present invention provides a process for saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, saliciding takes place prior to patterning one or more layers of a memory cell stack. The unpatterned layers protect the substrate between word lines from becoming salicided. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines, even in virtual ground arrays where there are no oxide island isolation regions between word lines. Potential advantages of such structures include reduced size, reduced number of processing steps, and reduced exposure to high temperature cycling.

摘要翻译： 本发明提供了一种在虚拟接地阵列闪存器件中对字线进行水印处理，而不引起位线之间的短路。 根据本发明的一个方面，在对存储单元堆叠的一层或多层进行构图之前进行水化。 未图案化的层保护字线之间的基板不会变成水银。 本发明提供具有掺杂和含水字线的虚拟接地阵列闪存器件，但是即使在字线之间没有氧化物岛隔离区域的虚拟接地阵列中也不会在位线之间发生短路。 这种结构的潜在优点包括减小的尺寸，减少的加工步骤数量以及降低暴露于高温循环。

公开(公告)号：US06455373B1

公开(公告)日：2002-09-24

申请号：US09834419

申请日：2001-04-12

申请人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

发明人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/11536

摘要： A plurality of core gate stacks and periphery gates on the substrate, each core gate stack and periphery gate having at least one side and first and second protective shoulders formed on said plurality of core gate stacks and periphery gates, such that a dopant can be implanted sequentially into source and drain regions of a substrate supporting the stacks to establish transistors and such that charge migration into said at least one side of the gate stacks during interlayer dielectric (ILD) formation and device metallization is prevented, at least the second shoulder being frabricated from at least one material selected from a group consisting essentially of nitride and silicon oxynitride (SiON).

摘要翻译： 在基板上的多个核心栅极叠层和周边栅极，每个芯栅极叠层和周边栅极具有形成在所述多个芯栅极叠层和外围栅极上的至少一个侧面和第一和第二保护肩部，使得掺杂剂可被植入 顺序地进入支撑堆叠的衬底的源极和漏极区域以建立晶体管，并且防止在层间电介质（ILD）形成和器件金属化期间电荷迁移到栅极叠层的所述至少一个侧面，至少第二肩部被破坏 选自由氮化物和氮氧化硅（SiON）组成的组中的至少一种材料。

公开(公告)号：US06369416B1

公开(公告)日：2002-04-09

申请号：US09404394

申请日：1999-09-23

申请人： Angela T. Hui ,  Tuan Duc Pham ,  Mark T. Ramsbey ,  Yu Sun

发明人： Angela T. Hui ,  Tuan Duc Pham ,  Mark T. Ramsbey ,  Yu Sun

IPC分类号： H01L2976

CPC分类号： H01L27/115 ,  H01L21/76804

摘要： A method and system for providing a contact in a semiconductor device including a plurality of gates is disclosed. The method and system include providing an insulating layer substantially surrounding at least a portion of the plurality of gates and providing at least one contact within the insulating layer. The contact has a side defining a sloped profile. The sloped profile includes an angle between the side of the contact and a surface of the substrate that is less than approximately eighty-eight degrees.

摘要翻译： 公开了一种用于在包括多个栅极的半导体器件中提供接触的方法和系统。 该方法和系统包括提供基本上围绕多个栅极的至少一部分的绝缘层，并且在绝缘层内提供至少一个触点。 触点具有限定倾斜轮廓的侧面。 倾斜轮廓包括接触侧面和基体表面之间的角度小于大约八十八度。

公开(公告)号：US06342415B1

公开(公告)日：2002-01-29

申请号：US09404395

申请日：1999-09-23

申请人： Angela T. Hui ,  Tuan Duc Pham ,  Mark T. Ramsbey ,  Yu Sun

发明人： Angela T. Hui ,  Tuan Duc Pham ,  Mark T. Ramsbey ,  Yu Sun

IPC分类号： H01L218238

CPC分类号： H01L21/31144 ,  H01L21/76816 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and system for providing a contact in a semiconductor device including a plurality of gates is disclosed. The method and system include providing an insulating layer substantially surrounding at least a portion of the plurality of gates and providing at least one contact within the insulating layer. The at least one contact has a reduced width that is less than approximately 0.28 microns

摘要翻译： 公开了一种用于在包括多个栅极的半导体器件中提供接触的方法和系统。 该方法和系统包括提供基本上围绕多个栅极的至少一部分的绝缘层，并且在绝缘层内提供至少一个触点。 所述至少一个接触件具有小于约0.28微米的减小的宽度

公开(公告)号：US06248627B1

公开(公告)日：2001-06-19

申请号：US09376658

申请日：1999-08-18

申请人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

发明人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/11536

摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.

摘要翻译： 制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。 然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。 然后将掺杂剂注入漏区。 在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

公开(公告)号：US06232630B1

公开(公告)日：2001-05-15

申请号：US09348583

申请日：1999-07-07

申请人： Mark T. Ramsbey ,  Tuan Pham ,  Yu Sun ,  Kenneth Wo-Wai Au ,  David H. Chi

发明人： Mark T. Ramsbey ,  Tuan Pham ,  Yu Sun ,  Kenneth Wo-Wai Au ,  David H. Chi

IPC分类号： H01L2972

CPC分类号： H01L29/42324

摘要： The reliability of a tunnel oxide is improved by light doping of the floating gate, as with phosphorous or arsenic atoms. Doping can be implemented by ion implantation or by in situ deposition. The relatively low dopant concentration further enhances charge retention on the floating gate.

摘要翻译： 隧道氧化物的可靠性通过浮栅的轻掺杂而改善，如同磷或砷原子一样。 掺杂可以通过离子注入或原位沉积来实现。 相对低的掺杂剂浓度进一步增强了浮栅上的电荷保持。

公开(公告)号：US06808996B1

公开(公告)日：2004-10-26

申请号：US09376659

申请日：1999-08-18

申请人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

发明人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.

摘要翻译： 制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。 然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。 然后将掺杂剂注入漏区。 在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

公开(公告)号：US06787840B1

公开(公告)日：2004-09-07

申请号：US09492931

申请日：2000-01-27

申请人： Tuan Duc Pham ,  Mark T. Ramsbey ,  Yu Sun ,  Chi Chang

发明人： Tuan Duc Pham ,  Mark T. Ramsbey ,  Yu Sun ,  Chi Chang

IPC分类号： H01L27108

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A semiconductor chip having a plurality of flash memory devices, shallow trench isolation in the periphery region, and LOCOS isolation in the core region. A hard mask is used first to create the shallow trench isolation. The LOCOS isolation is then created. Subsequent etching is used to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide barrier layer. A hard mask is used to prevent nitride contamination of the gate oxide layer. Periphery stacks have hate oxide layers of different thicknesses.

摘要翻译： 具有多个闪存器件的半导体芯片，周边区域中的浅沟槽隔离以及芯区域中的LOCOS隔离。 首先使用硬掩模来创建浅沟槽隔离。 然后创建LOCOS隔离。 随后的蚀刻用于去除桁条。 闪存能够使用浅沟槽隔离来限制侵占。 闪存也可以具有氮化的隧道氧化物阻挡层。 使用硬掩模来防止栅极氧化物层的氮化物污染。 外围堆叠具有不同厚度的恶性氧化物层。