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    Method for protecting gate edges from charge gain/loss in semiconductor device
    1.
    发明授权
    Method for protecting gate edges from charge gain/loss in semiconductor device 有权
    在半导体器件中保护栅极边缘免受电荷增益/损耗的方法

    公开(公告)号：US06808996B1

    公开(公告)日：2004-10-26

    申请号：US09376659

    申请日：1999-08-18

    申请人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

    发明人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

    IPC分类号： H01L21336

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.

    摘要翻译： 制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。 然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。 然后将掺杂剂注入漏区。 在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

    Semiconductor device having gate edges protected from charge gain/loss
    2.
    发明授权
    Semiconductor device having gate edges protected from charge gain/loss 有权
    具有防止电荷增益/损耗的栅极边缘的半导体器件

    公开(公告)号：US06455373B1

    公开(公告)日：2002-09-24

    申请号：US09834419

    申请日：2001-04-12

    申请人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

    发明人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

    IPC分类号： H01L21336

    CPC分类号： H01L27/11526 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/11536

    摘要： A plurality of core gate stacks and periphery gates on the substrate, each core gate stack and periphery gate having at least one side and first and second protective shoulders formed on said plurality of core gate stacks and periphery gates, such that a dopant can be implanted sequentially into source and drain regions of a substrate supporting the stacks to establish transistors and such that charge migration into said at least one side of the gate stacks during interlayer dielectric (ILD) formation and device metallization is prevented, at least the second shoulder being frabricated from at least one material selected from a group consisting essentially of nitride and silicon oxynitride (SiON).

    摘要翻译： 在基板上的多个核心栅极叠层和周边栅极，每个芯栅极叠层和周边栅极具有形成在所述多个芯栅极叠层和外围栅极上的至少一个侧面和第一和第二保护肩部，使得掺杂剂可被植入 顺序地进入支撑堆叠的衬底的源极和漏极区域以建立晶体管，并且防止在层间电介质（ILD）形成和器件金属化期间电荷迁移到栅极叠层的所述至少一个侧面，至少第二肩部被破坏 选自由氮化物和氮氧化硅（SiON）组成的组中的至少一种材料。

    Method for protecting gate edges from charge gain/loss in semiconductor device
    3.
    发明授权
    Method for protecting gate edges from charge gain/loss in semiconductor device 有权
    在半导体器件中保护栅极边缘免受电荷增益/损耗的方法

    公开(公告)号：US06248627B1

    公开(公告)日：2001-06-19

    申请号：US09376658

    申请日：1999-08-18

    申请人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

    发明人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

    IPC分类号： H01L21336

    CPC分类号： H01L27/11526 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/11536

    摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.

    摘要翻译： 制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。 然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。 然后将掺杂剂注入漏区。 在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

    Method of forming dual field isolation structures
    5.
    发明授权
    Method of forming dual field isolation structures 失效
    形成双场隔离结构的方法

    公开(公告)号：US5966618A

    公开(公告)日：1999-10-12

    申请号：US36288

    申请日：1998-03-06

    申请人： Yu Sun ,  Tuan D. Pham ,  Mark T. Ramsbey ,  Chi Chang

    发明人： Yu Sun ,  Tuan D. Pham ,  Mark T. Ramsbey ,  Chi Chang

    IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L27/08 ,  H01L27/105

    CPC分类号： H01L21/76221 ,  H01L27/105

    摘要： A method of providing thick and thin oxide structures reduces step changes between a core region and a peripheral region on an integrated circuit. Thin LOCOS structures are provided in a core region of a flash memory device, and thick LOCOS structures are provided in a peripheral region of the flash memory device. The device and process are not as susceptible to "race track" problems, "oxide" bump problems, and "stringer" problems. The process utilizes two separate nitride or hard mask layers.

    摘要翻译： 提供厚且薄的氧化物结构的方法减小了集成电路上的芯区域和周边区域之间的阶跃变化。 在闪速存储器件的核心区域中提供了薄的LOCOS结构，并且在闪速存储器件的外围区域中提供了厚的LOCOS结构。 设备和过程不容易受到“赛道”问题，“氧化物”碰撞问题和“纵梁”问题的影响。 该方法利用两个分开的氮化物或硬掩模层。

    Dual-purpose anti-reflective coating and spacer for flash memory and other dual gate technologies and method of forming
    6.
    发明授权
    Dual-purpose anti-reflective coating and spacer for flash memory and other dual gate technologies and method of forming 有权
    双用途抗反射涂层和闪存间隔器等双栅技术及成型方法

    公开(公告)号：US06798002B1

    公开(公告)日：2004-09-28

    申请号：US09607675

    申请日：2000-06-30

    申请人： Robert B. Ogle, Jr. ,  Tuan D. Pham ,  Mark T. Ramsbey

    发明人： Robert B. Ogle, Jr. ,  Tuan D. Pham ,  Mark T. Ramsbey

    IPC分类号： H01L27108

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

    摘要： A dual gate semiconductor device, such as a flash memory semiconductor device, whose plurality of dual gate sidewall spacer structure is formed by a first and second anti-reflection fabrication process. The sidewall spacers of the dual transistor gate structures in the core memory region are left coated with the second anti-reflective coating material, after being used for gate patterning, to act as sidewall spacers for use in subsequent ion implant and salicidation fabrication steps. The second anti-reflective coating material is selected from a material group such as silicon oxynitride (SiON), silicon nitride (Si3N4), and silicon germanium (SiGe), or other anti-reflective coating material having optical properties and that are compatible with the subsequent implant and salicidation steps.

    摘要翻译： 诸如闪存半导体器件的双栅极半导体器件，其多个双栅极侧壁间隔结构通过第一和第二抗反射制造工艺形成。 核心存储器区域中的双晶体管栅极结构的侧壁间隔物在用于栅极图案化之后被第二抗反射涂层材料涂覆以用作用于后续离子注入和盐化制造步骤的侧壁间隔物。 第二抗反射涂层材料选自诸如氮氧化硅（SiON），氮化硅（Si 3 N 4）和硅锗（SiGe）的材料组或具有光学性质的其它抗反射涂层材料，并且与 随后的植入和盐化步骤。

    Method and system for providing tapered shallow trench isolation structure profile
    7.
    发明授权
    Method and system for providing tapered shallow trench isolation structure profile 失效
    提供锥形浅沟槽隔离结构轮廓的方法和系统

    公开(公告)号：US5998301A

    公开(公告)日：1999-12-07

    申请号：US993252

    申请日：1997-12-18

    申请人： Tuan D. Pham ,  Angela T. Hui ,  Kashmir Sahota

    发明人： Tuan D. Pham ,  Angela T. Hui ,  Kashmir Sahota

    IPC分类号： H01L21/8247 ,  H01L21/76 ,  H01L21/762 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/308

    CPC分类号： H01L21/76232 ,  H01L21/76237

    摘要： A method and system for providing a shallow trench isolation structure profile on a semiconductor is disclosed. The method and system includes patterning a mask on the semiconductor substrate, etching the mask such that the mask has sloped sides, etching the semiconductor substrate to form a trench whereby the trench has tapered sides, and planarizing the semiconductor substrate to optimize the trench depth and the width of the trench opening for subsequent processes. According to the method and system disclosed herein, the present invention allows a shallow trench isolation structure profile to be formed which has tapered sides.

    摘要翻译： 公开了一种用于在半导体上提供浅沟槽隔离结构轮廓的方法和系统。 该方法和系统包括在半导体衬底上图案化掩模，蚀刻掩模使得掩模具有倾斜的侧面，蚀刻半导体衬底以形成沟槽，由此沟槽具有锥形侧面，并平坦化半导体衬底以优化沟槽深度， 用于后续处理的沟槽开口的宽度。 根据本文公开的方法和系统，本发明允许形成具有锥形侧面的浅沟槽隔离结构轮廓。

    Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices
    8.
    发明授权
    Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices 失效
    在非易失性存储器半导体器件中形成浮置栅极的方法和装置

    公开(公告)号：US06034394A

    公开(公告)日：2000-03-07

    申请号：US992950

    申请日：1997-12-18

    申请人： Mark Ramsbey ,  Tuan D. Pham ,  Yu Sun ,  Kenneth W. Au

    发明人： Mark Ramsbey ,  Tuan D. Pham ,  Yu Sun ,  Kenneth W. Au

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

    摘要： Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates, by advantageously reducing the thickness of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.

    摘要翻译： 提供了在非易失性存储器半导体器件中制造浮置/控制栅极配置期间增加处理控制的方法和装置。 通过有利地减小浮动栅极的厚度，这些方法和布置有效地降低了归因于相邻浮动栅极之间的空间的拓扑的严重性。 改变的拓扑允许随后形成的控制栅极形成而没有显着的表面凹陷。 控制栅中的显着的表面凹陷可能导致在控制栅上形成的硅化物层中的裂纹。 裂纹通常发生在半导体器件的随后热处理期间。 因此，所公开的方法和布置防止了控制栅极上的硅化物层的破裂，这可以通过增加控制栅极布置的电阻来影响半导体器件的性能。

    Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices
    9.
    发明授权
    Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices 有权
    在非易失性存储器半导体器件中形成浮置栅极的方法和装置

    公开(公告)号：US06274433B1

    公开(公告)日：2001-08-14

    申请号：US09476121

    申请日：2000-01-03

    申请人： Mark Ramsbey ,  Tuan D. Pham ,  Yu Sun ,  Kenneth W. Au

    发明人： Mark Ramsbey ,  Tuan D. Pham ,  Yu Sun ,  Kenneth W. Au

    IPC分类号： H01L218247

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

    摘要： Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates, by advantageously reducing the thickness of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.

    摘要翻译： 提供了在非易失性存储器半导体器件中制造浮置/控制栅极配置期间增加处理控制的方法和装置。 通过有利地减小浮动栅极的厚度，这些方法和布置有效地降低了归因于相邻浮动栅极之间的空间的拓扑的严重性。 改变的拓扑允许随后形成的控制栅极形成而没有显着的表面凹陷。 控制栅中的显着的表面凹陷可能导致在控制栅上形成的硅化物层中的裂纹。 裂纹通常发生在半导体器件的随后热处理期间。 因此，所公开的方法和布置防止了控制栅极上的硅化物层的破裂，这可以通过增加控制栅极布置的电阻来影响半导体器件的性能。