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    Method for fabricating a semiconductor device
    3.
    发明授权
    Method for fabricating a semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US08530316B2

    公开(公告)日：2013-09-10

    申请号：US13736453

    申请日：2013-01-08

    申请人： Yu-Hung Cheng ,  Jhi-Cherng Lu ,  Ming-Hua Yu ,  Chii-Horng Li ,  Tze-Liang Lee

    发明人： Yu-Hung Cheng ,  Jhi-Cherng Lu ,  Ming-Hua Yu ,  Chii-Horng Li ,  Tze-Liang Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L21/20 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66477 ,  H01L29/7848

    摘要： A method for fabricating a semiconductor device, the method including growing a first semiconductor structure comprising a first semiconductor material on a surface of a substrate, wherein growing the first semiconductor structure includes forming a semiconductor particle comprising the first semiconductor material on a second semiconductor structure of the semiconductor device. The method further includes forming a protection layer of a second semiconductor material on the first semiconductor structure, wherein forming the protection layer includes forming the protection layer on the semiconductor particle. The method further includes removing a portion of the protection layer, wherein removing the portion of the protection layer includes fully removing the protection layer on the semiconductor particle and the semiconductor particle.

    摘要翻译： 一种制造半导体器件的方法，所述方法包括在衬底的表面上生长包括第一半导体材料的第一半导体结构，其中生长第一半导体结构包括在第二半导体结构的第二半导体结构上形成包含第一半导体材料的半导体粒子 半导体器件。 该方法还包括在第一半导体结构上形成第二半导体材料的保护层，其中形成保护层包括在半导体颗粒上形成保护层。 该方法还包括去除保护层的一部分，其中去除保护层的部分包括完全去除半导体颗粒和半导体颗粒上的保护层。

    Reducing Variation by Using Combination Epitaxy Growth
    4.
    发明申请
    Reducing Variation by Using Combination Epitaxy Growth 有权
    通过组合外延生长减少变异

    公开(公告)号：US20110287611A1

    公开(公告)日：2011-11-24

    申请号：US13030850

    申请日：2011-02-18

    申请人： Yu-Hung Cheng ,  Chii-Horng Li ,  Tze-Liang Lee ,  Yi-Hung Lin

    发明人： Yu-Hung Cheng ,  Chii-Horng Li ,  Tze-Liang Lee ,  Yi-Hung Lin

    IPC分类号： H01L21/20

    CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/7848

    摘要： A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (E/G) ratio of process gases used in the first growth stage; and performing a second growth stage with a second E/G ratio of process gases used in the second growth stage different from the first E/G ratio.

    摘要翻译： 一种用于形成半导体结构的方法包括在晶片上的半导体衬底上形成栅叠层; 在所述半导体衬底中形成凹槽并邻近所述栅叠层; 以及进行选择性外延生长以在所述凹部中生长半导体材料以形成外延区域。 执行选择性外延生长的步骤包括以第一生长阶段中使用的工艺气体的第一生长蚀刻（E / G）比率进行第一生长阶段; 以及在与第一E / G比不同的第二生长阶段中使用的处理气体的第二E / G比进行第二生长阶段。

    Reducing variation by using combination epitaxy growth
    7.
    发明授权
    Reducing variation by using combination epitaxy growth 有权
    通过组合外延生长减少变异

    公开(公告)号：US08828850B2

    公开(公告)日：2014-09-09

    申请号：US13030850

    申请日：2011-02-18

    申请人： Yu-Hung Cheng ,  Chii-Horng Li ,  Tze-Liang Lee ,  Yi-Hung Lin

    发明人： Yu-Hung Cheng ,  Chii-Horng Li ,  Tze-Liang Lee ,  Yi-Hung Lin

    IPC分类号： H01L21/20 ,  H01L21/36

    CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/7848

    摘要： A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (E/G) ratio of process gases used in the first growth stage; and performing a second growth stage with a second E/G ratio of process gases used in the second growth stage different from the first E/G ratio.

    摘要翻译： 一种用于形成半导体结构的方法包括在晶片上的半导体衬底上形成栅叠层; 在所述半导体衬底中形成凹槽并邻近所述栅叠层; 以及进行选择性外延生长以在所述凹部中生长半导体材料以形成外延区域。 执行选择性外延生长的步骤包括以第一生长阶段中使用的工艺气体的第一生长蚀刻（E / G）比率进行第一生长阶段; 以及在与第一E / G比不同的第二生长阶段中使用的处理气体的第二E / G比进行第二生长阶段。

    Strained semiconductor device with facets
    8.
    发明授权
    Strained semiconductor device with facets 有权
    应变半导体器件与面

    公开(公告)号：US08455930B2

    公开(公告)日：2013-06-04

    申请号：US12984877

    申请日：2011-01-05

    申请人： Yu-Hung Cheng ,  Chii-Horng Li ,  Tze-Liang Lee

    发明人： Yu-Hung Cheng ,  Chii-Horng Li ,  Tze-Liang Lee

    IPC分类号： H01L27/085

    CPC分类号： H01L29/66636 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/78 ,  H01L29/7848

    摘要： A semiconductor device having a substrate including a major surface, a gate stack comprising a sidewall over the substrate and a spacer over the substrate adjoining the sidewall of the gate stack. The spacer having a bottom surface having an outer point that is the point on the bottom surface farthest from the gate stack. An isolation structure in the substrate on one side of the gate stack has an outer edge closest to the spacer. A strained material below the major surface of the substrate disposed between the spacer and the isolation structure having an upper portion and a lower portion separated by a transition plane at an acute angle to the major surface of the substrate.

    摘要翻译： 一种具有包括主表面的衬底的半导体器件，包括在衬底上的侧壁的栅极堆叠以及与栅极堆叠的侧壁相邻的衬底上的间隔物。 该间隔件具有底表面，该外表面是位于最远离该栅极叠层的底表面上的点。 在栅极堆叠的一侧上的衬底中的隔离结构具有最靠近间隔物的外边缘。 位于衬垫的主表面之下的应变材料设置在间隔件和隔离结构之间，该上表面和隔离结构具有与衬底的主表面成锐角的过渡面分开的上部和下部。

    Selective Etching in the Formation of Epitaxy Regions in MOS Devices
    10.
    发明申请
    Selective Etching in the Formation of Epitaxy Regions in MOS Devices 有权
    MOS器件中外延区形成中的选择性蚀刻

    公开(公告)号：US20110287600A1

    公开(公告)日：2011-11-24

    申请号：US12784344

    申请日：2010-05-20

    申请人： Yu-Hung Cheng ,  Chii-Horng Li ,  Tze-Liang Lee

    发明人： Yu-Hung Cheng ,  Chii-Horng Li ,  Tze-Liang Lee

    IPC分类号： H01L21/336 ,  H01L21/20

    CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/1116 ,  H01L29/7848

    摘要： A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. After the step of performing the selective epitaxial growth, a selective etch-back is performed to the epitaxy region. The selective etch-back is performed using process gases comprising a first gas for growing the semiconductor material, and a second gas for etching the epitaxy region.

    摘要翻译： 一种用于形成半导体结构的方法包括在半导体衬底上形成栅叠层; 在所述半导体衬底中形成凹槽并邻近所述栅叠层; 以及进行选择性外延生长以在所述凹部中生长半导体材料以形成外延区域。 在执行选择性外延生长的步骤之后，对外延区进行选择性回蚀。 使用包括用于生长半导体材料的第一气体的处理气体和用于蚀刻外延区域的第二气体来执行选择性回蚀。