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    Method and apparatus for adjusting phase of sampling frequency of ADC
    1.
    发明授权
    Method and apparatus for adjusting phase of sampling frequency of ADC 有权
    调整ADC采样频率相位的方法和装置

    公开(公告)号：US07535982B2

    公开(公告)日：2009-05-19

    申请号：US11160516

    申请日：2005-06-27

    申请人： Yu-Pin Chou ,  An-Shih Lee ,  Hsien-Chun Chang

    发明人： Yu-Pin Chou ,  An-Shih Lee ,  Hsien-Chun Chang

    IPC分类号： H04L7/00

    CPC分类号： G09G5/008 ,  G09G3/2096 ,  H03M1/1255 ,  H04L7/007 ,  H04L7/0334 ,  H04L7/0337

    摘要： A method for adjusting a phase of a sampling frequency of ADC is disclosed. The method includes converting an analog signal into a first digital signal according to a first phase of the sampling frequency during a first time interval; calculating a first value according to the first digital signal; converting the analog signal into a second digital signal according to a second phase of the sampling frequency during a second time interval; calculating a second value according to the second digital signal; and adjusting the phase of the sampling frequency according to the first value and the second value.

    摘要翻译： 公开了一种调整ADC采样频率相位的方法。 该方法包括在第一时间间隔期间根据采样频率的第一相位将模拟信号转换为第一数字信号; 根据第一数字信号计算第一值; 在第二时间间隔期间根据采样频率的第二相位将模拟信号转换成第二数字信号; 根据第二数字信号计算第二值; 以及根据第一值和第二值调整采样频率的相位。

    METHOD AND APPARATUS FOR ADJUSTING PHASE OF SAMPLING FREQUENCY OF ADC
    2.
    发明申请
    METHOD AND APPARATUS FOR ADJUSTING PHASE OF SAMPLING FREQUENCY OF ADC 有权
    用于调节ADC采样频率的方法和装置

    公开(公告)号：US20060056558A1

    公开(公告)日：2006-03-16

    申请号：US11160516

    申请日：2005-06-27

    申请人： Yu-Pin Chou ,  An-Shih Lee ,  Hsien-Chun Chang

    发明人： Yu-Pin Chou ,  An-Shih Lee ,  Hsien-Chun Chang

    IPC分类号： H04L7/00

    CPC分类号： G09G5/008 ,  G09G3/2096 ,  H03M1/1255 ,  H04L7/007 ,  H04L7/0334 ,  H04L7/0337

    摘要： A method for adjusting a phase of a sampling frequency of ADC is disclosed. The method includes converting an analog signal into a first digital signal according to a first phase of the sampling frequency during a first time interval; calculating a first value according to the first digital signal; converting the analog signal into a second digital signal according to a second phase of the sampling frequency during a second time interval; calculating a second value according to the second digital signal; and adjusting the phase of the sampling frequency according to the first value and the second value.

    摘要翻译： 公开了一种调整ADC采样频率相位的方法。 该方法包括在第一时间间隔期间根据采样频率的第一相位将模拟信号转换为第一数字信号; 根据第一数字信号计算第一值; 在第二时间间隔期间根据采样频率的第二相位将模拟信号转换成第二数字信号; 根据第二数字信号计算第二值; 以及根据第一值和第二值调整采样频率的相位。

    DEVICE AND METHOD FOR CONTROLLING FRAME INPUT AND OUTPUT
    3.
    发明申请
    DEVICE AND METHOD FOR CONTROLLING FRAME INPUT AND OUTPUT 有权
    用于控制框架输入和输出的装置和方法

    公开(公告)号：US20100188574A1

    公开(公告)日：2010-07-29

    申请号：US12692389

    申请日：2010-01-22

    申请人： Chia-Lung HUNG ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

    发明人： Chia-Lung HUNG ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

    IPC分类号： H04N9/64 ,  H04N5/04

    CPC分类号： H04N7/0105 ,  H04N7/0132

    摘要： A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.

    摘要翻译： 用于控制帧输入和输出的装置和方法被应用于从源设备接收图像数据并将图像数据输出到目的地设备，该设备包括缓冲器，缓冲器控制电路和帧写入控制器。 输入像素时钟不等于输出像素时钟。 帧写入控制器根据输入DE和输出DE生成写许可信号。 缓冲器控制电路根据输入DE和写允许信号产生写控制信号，并根据输出DE生成读控制信号。 缓冲器根据写控制信号和输入像素时钟从源装置接收图像数据，并根据读控制信号和输出像素时钟将图像数据输出到目的地装置。

    Power-on reset circuit
    6.
    发明授权
    Power-on reset circuit 有权
    上电复位电路

    公开(公告)号：US08446189B2

    公开(公告)日：2013-05-21

    申请号：US12794227

    申请日：2010-06-04

    申请人： Yu-Pin Chou ,  Hsien-Chun Chang ,  Wen-Che Wu

    发明人： Yu-Pin Chou ,  Hsien-Chun Chang ,  Wen-Che Wu

    IPC分类号： H03L7/00

    CPC分类号： H03K17/20

    摘要： A power-on reset circuit includes a clamping signal generator and a determining device. The clamping signal generator is adapted to receive a trigger signal, and generates a clamping signal with reference to the trigger signal. The clamping signal generator includes an output unit for generating the clamping signal according to a feedback signal, and a feedback unit for generating the feedback signal according to first and second intermediate signals. The first intermediate signal is generated with reference to the clamping signal. The second intermediate signal is generated according to the trigger signal. The determining device is adapted to receive the trigger signal, is coupled to the clamping signal generator for receiving the clamping signal therefrom, and is operable to generate a reset signal according to the trigger signal and the clamping signal.

    摘要翻译： 上电复位电路包括钳位信号发生器和确定装置。 钳位信号发生器适于接收触发信号，并且参考触发信号产生钳位信号。 钳位信号发生器包括用于根据反馈信号产生钳位信号的输出单元和用于根据第一和第二中间信号产生反馈信号的反馈单元。 参考钳位信号产生第一中间信号。 根据触发信号产生第二中间信号。 确定装置适于接收触发信号，耦合到钳位信号发生器用于从其接收钳位信号，并且可操作以根据触发信号和钳位信号产生复位信号。

    POWER-ON RESET CIRCUIT
    7.
    发明申请
    POWER-ON RESET CIRCUIT 有权
    上电复位电路

    公开(公告)号：US20100308877A1

    公开(公告)日：2010-12-09

    申请号：US12794227

    申请日：2010-06-04

    申请人： Yu-Pin Chou ,  Hsien-Chun Chang ,  Wen-Che Wu

    发明人： Yu-Pin Chou ,  Hsien-Chun Chang ,  Wen-Che Wu

    IPC分类号： H03L7/00

    CPC分类号： H03K17/20

    摘要： A power-on reset circuit includes a clamping signal generator and a determining device. The clamping signal generator is adapted to receive a trigger signal, and generates a clamping signal with reference to the trigger signal. The clamping signal generator includes an output unit for generating the clamping signal according to a feedback signal, and a feedback unit for generating the feedback signal according to first and second intermediate signals. The first intermediate signal is generated with reference to the clamping signal. The second intermediate signal is generated according to the trigger signal. The determining device is adapted to receive the trigger signal, is coupled to the clamping signal generator for receiving the clamping signal therefrom, and is operable to generate a reset signal according to the trigger signal and the clamping signal.

    摘要翻译： 上电复位电路包括钳位信号发生器和确定装置。 钳位信号发生器适于接收触发信号，并且参考触发信号产生钳位信号。 钳位信号发生器包括用于根据反馈信号产生钳位信号的输出单元和用于根据第一和第二中间信号产生反馈信号的反馈单元。 参考钳位信号产生第一中间信号。 根据触发信号产生第二中间信号。 确定装置适于接收触发信号，耦合到钳位信号发生器用于从其接收钳位信号，并且可操作以根据触发信号和钳位信号产生复位信号。

    Device and method for controlling frame input and output
    8.
    发明授权
    Device and method for controlling frame input and output 有权
    用于控制帧输入和输出的装置和方法

    公开(公告)号：US08471859B2

    公开(公告)日：2013-06-25

    申请号：US12692389

    申请日：2010-01-22

    申请人： Chia-Lung Hung ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

    发明人： Chia-Lung Hung ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

    IPC分类号： G09G5/39 ,  G09G5/36 ,  G06F12/02 ,  H04N7/01

    CPC分类号： H04N7/0105 ,  H04N7/0132

    摘要： A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.

    摘要翻译： 用于控制帧输入和输出的装置和方法被应用于从源设备接收图像数据并将图像数据输出到目的地设备，该设备包括缓冲器，缓冲器控制电路和帧写入控制器。 输入像素时钟不等于输出像素时钟。 帧写入控制器根据输入DE和输出DE生成写许可信号。 缓冲器控制电路根据输入DE和写允许信号产生写控制信号，并根据输出DE生成读控制信号。 缓冲器根据写控制信号和输入像素时钟从源装置接收图像数据，并根据读控制信号和输出像素时钟将图像数据输出到目的地装置。

    Mode detecting circuit and method thereof
    9.
    发明授权
    Mode detecting circuit and method thereof 有权
    模式检测电路及其方法

    公开(公告)号：US09082332B2

    公开(公告)日：2015-07-14

    申请号：US12128372

    申请日：2008-05-28

    申请人： Yu-Pin Chou ,  Szu-Ping Chen ,  Yu Jen Lin

    发明人： Yu-Pin Chou ,  Szu-Ping Chen ,  Yu Jen Lin

    IPC分类号： G09G5/02 ,  G09G5/00

    CPC分类号： G06T1/60 ,  G09G3/28 ,  G09G3/36 ,  G09G5/005 ,  G09G2310/08 ,  G09G2340/0414 ,  G09G2340/0421

    摘要： The invention discloses a mode detection circuit and a method thereof, for detecting an image signal, the image signal includes a horizontal resolution and the vertical resolution. The mode detection circuit includes a measuring unit, a calculation unit, and a decision unit. The measuring unit receives a clock signal and is used to count the clock signal to output a first counting value and the second counting value. The calculation unit is used to perform the calculation with the first counting value and the second counting value and thereby outputting a calculating value, wherein the calculating value outputted by the calculation unit is corresponding to the ratio of the first counting value to the second counting value. The decision unit is used to determine the horizontal resolution or the vertical resolution according to the calculating value.

    摘要翻译： 本发明公开了一种模式检测电路及其方法，用于检测图像信号，图像信号包括水平分辨率和垂直分辨率。 模式检测电路包括测量单元，计算单元和判定单元。 测量单元接收时钟信号，并用于对时钟信号进行计数以输出第一计数值和第二计数值。 计算单元用于执行具有第一计数值和第二计数值的计算，从而输出计算值，其中由计算单元输出的计算值对应于第一计数值与第二计数值的比率 。 决策单元用于根据计算值确定水平分辨率或垂直分辨率。

    Display processing device and timing controller thereof
    10.
    发明授权
    Display processing device and timing controller thereof 有权

    公开(公告)号：US08514206B2

    公开(公告)日：2013-08-20

    申请号：US12314601

    申请日：2008-12-12

    申请人： Yu-Pin Chou ,  Tzuo-Bo Lin ,  Ming-Syun Wu

    发明人： Yu-Pin Chou ,  Tzuo-Bo Lin ,  Ming-Syun Wu

    IPC分类号： G09G5/00

    CPC分类号： G09G5/006 ,  G09G5/005 ,  G09G2370/12

    摘要： A timing controller for a display processing device includes: a plurality of predetermined pins for receiving an image signal by a pin-share method, wherein the image signal is a first format image signal or a second format image signal; a detector coupled to the predetermined pins and for detecting at least one of the predetermined pins to determine whether the image signal is the first format image signal or the second format image signal and outputting a detection result; and a processor coupled to the detector and for processing the image signal according to the detection result to generate and output a timing control signal.