Photomask for test wafers
    1.
    发明授权
    Photomask for test wafers 失效
    用于测试晶片的光掩模

    公开(公告)号:US06841405B2

    公开(公告)日:2005-01-11

    申请号:US10269268

    申请日:2002-10-10

    IPC分类号: G01R31/28 H01L21/00

    CPC分类号: G01R31/2812 G01R31/2818

    摘要: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.

    摘要翻译: 电子设备的制造方法是使用测试结构提高测试效率并提高产量。 该制造方法使用设置在形成于基板上的绝缘层上的第一引线和与基板电连接并设置在绝缘层上的第二引线进行测试,并基于制造试验的结果来管理电子设备 电子设备。 该制造方法包括通过测量第一引线的两端之间的电阻和通过测量第一和第二引线是否短路的步骤来测试第一引线是否断开的步骤 第一引线与基板之间的电阻。

    Method of testing electronic devices
    2.
    发明授权
    Method of testing electronic devices 失效
    电子设备测试方法

    公开(公告)号:US06770496B2

    公开(公告)日:2004-08-03

    申请号:US10269411

    申请日:2002-10-10

    IPC分类号: H01L2166

    CPC分类号: G01R31/2812 G01R31/2818

    摘要: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.

    摘要翻译: 电子设备的制造方法是使用测试结构提高测试效率并提高产量。 该制造方法使用设置在形成于基板上的绝缘层上的第一引线和与基板电连接并设置在绝缘层上的第二引线进行测试,并基于制造试验的结果来管理电子设备 电子设备。 该制造方法包括通过测量第一引线的两端之间的电阻和通过测量第一和第二引线是否短路的步骤来测试第一引线是否断开的步骤 第一引线与基板之间的电阻。

    Method for test conditions
    3.
    发明授权
    Method for test conditions 失效
    测试条件的方法

    公开(公告)号:US06895346B2

    公开(公告)日:2005-05-17

    申请号:US10269127

    申请日:2002-10-10

    IPC分类号: G01R31/28 G06F19/00 H01L21/00

    CPC分类号: G01R31/2812 G01R31/2818

    摘要: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.

    摘要翻译: 电子设备的制造方法是使用测试结构提高测试效率并提高产量。 该制造方法使用设置在形成于基板上的绝缘层上的第一引线和与基板电连接并设置在绝缘层上的第二引线进行测试,并基于制造试验的结果来管理电子设备 电子设备。 该制造方法包括通过测量第一引线的两端之间的电阻和通过测量第一和第二引线是否短路的步骤来测试第一引线是否断开的步骤 第一引线与基板之间的电阻。

    Method of testing electronic devices indicating short-circuit
    4.
    发明授权
    Method of testing electronic devices indicating short-circuit 失效
    测试表示短路的电子设备的方法

    公开(公告)号:US06771077B2

    公开(公告)日:2004-08-03

    申请号:US10126263

    申请日:2002-04-19

    IPC分类号: G01R3102

    CPC分类号: G01R31/2812 G01R31/2818

    摘要: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.

    摘要翻译: 电子设备的制造方法是使用测试结构提高测试效率并提高产量。 该制造方法使用设置在形成于基板上的绝缘层上的第一引线和与基板电连接并设置在绝缘层上的第二引线进行测试,并基于制造试验的结果来管理电子设备 电子设备。 该制造方法包括通过测量第一引线的两端之间的电阻和通过测量第一和第二引线是否短路的步骤来测试第一引线是否断开的步骤 第一引线与基板之间的电阻。

    System for testing electronic devices
    5.
    发明授权
    System for testing electronic devices 失效
    电子设备测试系统

    公开(公告)号:US06780660B2

    公开(公告)日:2004-08-24

    申请号:US10269199

    申请日:2002-10-10

    IPC分类号: H01L2166

    CPC分类号: G01R31/2812 G01R31/2818

    摘要: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.

    摘要翻译: 电子设备的制造方法是使用测试结构提高测试效率并提高产量。 该制造方法使用设置在形成于基板上的绝缘层上的第一引线和与基板电连接并设置在绝缘层上的第二引线进行测试,并基于制造试验的结果来管理电子设备 电子设备。 该制造方法包括通过测量第一引线的两端之间的电阻和通过测量第一和第二引线是否短路的步骤来测试第一引线是否断开的步骤 第一引线与基板之间的电阻。

    Defective-ratio predicting method, defective-ratio predicting program, managing method for semiconductor manufacturing apparatus, and manufacturing method for semiconductor device
    6.
    发明授权
    Defective-ratio predicting method, defective-ratio predicting program, managing method for semiconductor manufacturing apparatus, and manufacturing method for semiconductor device 有权
    缺陷比预测方法,缺陷比预测程序,半导体制造装置的管理方法以及半导体装置的制造方法

    公开(公告)号:US08612811B2

    公开(公告)日:2013-12-17

    申请号:US13119633

    申请日:2009-09-04

    IPC分类号: G11C29/56

    摘要: In a managing system for a semiconductor manufacturing apparatus, a predicting unit 121 predicts a characteristic defective ratio and a foreign-substance defective ratio of each process obtains an actual defective ratio of each fail bit mode and a critical area of each process and each fail bit mode, calculates the number of foreign substances of each process by using the actual defective ratio of each fail bit mode and the critical area of each process and each fail bit mode, the fail bit mode being except for an arbitrary fail bit mode, calculates a foreign-substance defective ratio of each process and a foreign-substance defective ratio of each fail bit mode by using the number of foreign substances, and calculates a characteristic defective ratio of the arbitrary fail bit mode based on the foreign-substance defective ratio and actual defective ratio of each fail bit mode.

    摘要翻译: 在半导体制造装置的管理系统中,预测单元121预测每个处理的特征缺陷率和异物缺陷率,获得每个故障位模式和每个处理的临界区域的实际缺陷率以及每个故障位 模式,通过使用每个故障位模式的实际故障率和每个过程的关键区域以及每个故障位模式来计算每个过程的异物数量,故障位模式除了任意故障位模式,计算出 通过使用异物数量,每个处理的异物缺陷率和每个故障位模式的异物缺陷率,并且基于异物缺陷率和实际值计算任意故障位模式的特征缺陷率 每个故障位模式的故障率。

    DEFECTIVE-RATIO PREDICTING METHOD, DEFECTIVE-RATIO PREDICTING PROGRAM, MANAGING METHOD FOR SEMICONDUCTOR MANUFACTURING APPARATUS, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
    7.
    发明申请
    DEFECTIVE-RATIO PREDICTING METHOD, DEFECTIVE-RATIO PREDICTING PROGRAM, MANAGING METHOD FOR SEMICONDUCTOR MANUFACTURING APPARATUS, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE 有权
    缺陷比预测方法,缺陷比预测方案,半导体制造装置的管理方法和半导体器件的制造方法

    公开(公告)号:US20110172806A1

    公开(公告)日:2011-07-14

    申请号:US13119633

    申请日:2009-09-04

    IPC分类号: G06F19/00

    摘要: In a managing system for a semiconductor manufacturing apparatus, a predicting unit 121 predicts a characteristic defective ratio and a foreign-substance defective ratio of each process obtains an actual defective ratio of each fail bit mode and a critical area of each process and each fail bit mode, calculates the number of foreign substances of each process by using the actual defective ratio of each fail bit mode and the critical area of each process and each fail bit mode, the fail bit mode being except for an arbitrary fail bit mode, calculates a foreign-substance defective ratio of each process and a foreign-substance defective ratio of each fail bit mode by using the number of foreign substances, and calculates a characteristic defective ratio of the arbitrary fail bit mode based on the foreign-substance defective ratio and actual defective ratio of each fail bit mode.

    摘要翻译: 在半导体制造装置的管理系统中,预测单元121预测每个处理的特征缺陷率和异物缺陷率,获得每个故障位模式和每个处理的临界区域的实际缺陷率以及每个故障位 模式,通过使用每个故障位模式的实际故障率和每个过程的关键区域以及每个故障位模式来计算每个过程的异物数量,故障位模式除了任意故障位模式,计算出 通过使用异物数量,每个处理的异物缺陷率和每个故障位模式的异物缺陷率,并且基于异物缺陷率和实际值计算任意故障位模式的特征缺陷率 每个故障位模式的故障率。