公开(公告)号：US06537884B1

公开(公告)日：2003-03-25

申请号：US09389381

申请日：1999-09-03

申请人： Yukiaki Yogo ,  Shigemitsu Fukatsu

发明人： Yukiaki Yogo ,  Shigemitsu Fukatsu

IPC分类号： H01L21336

CPC分类号： H01L29/66659 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665

摘要： A semiconductor device having an offset-gate structure, which can achieve a release of an electric field concentration and a lowering a transistor resistance at the same time. A semiconductor device has the offset-gate structure in which an offset region, at which a gate portion is not formed, is formed between an end of the gate portion and a drain on a silicon substrate. Surfaces of a source, the drain and a gate electrode of the gate portion are silicides to reduce a transistor resistance. Whereas a surface of the offset region formed between the gate portion and the drain does not include silicide. to prevent a potential of an end portion of the gate portion from being identical to a potential of the drain due to silicide. Therefore, it can achieve a release of an electric field concentration and a lowering a transistor resistance at the same time.

摘要翻译： 具有偏移栅极结构的半导体器件可同时实现电场浓度的释放和降低晶体管电阻。 半导体器件具有偏移栅结构，其中在栅极部分的端部和硅衬底上的漏极之间形成有未形成栅极部分的偏移区域。 栅极部分的源极，漏极和栅电极的表面是硅化物，以减小晶体管电阻。 而形成在栅极部分和漏极之间的偏移区域的表面不包括硅化物。 以防止栅极部分的端部的电位与由硅化物引起的漏极的电位相同。 因此，能够同时实现电场浓度的释放和晶体管电阻的降低。

公开(公告)号：US5986302A

公开(公告)日：1999-11-16

申请号：US18305

申请日：1998-02-03

申请人： Shigemitsu Fukatsu ,  Tsutomu Kawaguchi ,  Takuya Okuno ,  Yukiaki Yogo

发明人： Shigemitsu Fukatsu ,  Tsutomu Kawaguchi ,  Takuya Okuno ,  Yukiaki Yogo

IPC分类号： H01L21/28 ,  H01L29/788 ,  H01L29/76 ,  H01L29/792

CPC分类号： H01L21/28273 ,  H01L29/7885

摘要： A floating gate of a semiconductor memory device has a gate bird beak on an end portion thereof. Further, a positional relationship between the floating gate and a drain is controlled such that a depletion layer formed within the drain in a non-selected state of the semiconductor memory device faces the gate bird beak without interposing the drain therebetween. Accordingly, drain disturbance can be efficiently prevented.

摘要翻译： 半导体存储器件的浮置栅极在其端部具有栅极鸟嘴。 此外，控制浮置栅极和漏极之间的位置关系，使得形成在半导体存储器件的未选择状态的漏极内的耗尽层面对栅极鸟嘴而不在其间插入漏极。 因此，能够有效地防止漏极干扰。

公开(公告)号：US20060170406A1

公开(公告)日：2006-08-03

申请号：US11340545

申请日：2006-01-27

申请人： Takashi Kawashima ,  Yasuaki Makino ,  Masato Ishihara ,  Yukiaki Yogo ,  Satoshi Oohira

发明人： Takashi Kawashima ,  Yasuaki Makino ,  Masato Ishihara ,  Yukiaki Yogo ,  Satoshi Oohira

IPC分类号： G05F1/635

CPC分类号： G05F1/635 ,  H01L43/065 ,  H01L43/14

摘要： An N-type epitaxial layer is formed on a p-type silicon substrate. Four N+ regions (diffusion regions used as electrodes) are formed in the N-type epitaxial layer. An insulation layer having a fixed depth is formed around each of the N+ regions on a principal surface of an epitaxial layer. The insulation layer restricts a current path region formed between the N+ regions. Side surfaces of the N+ regions are covered by the insulation layer. The N+ regions are brought into contact with the epitaxial layer by a bottom surface exposed from the insulation layer.

摘要翻译： 在p型硅衬底上形成N型外延层。 在N型外延层中形成四个N + +区域（用作电极的扩散区）。 在外延层的主表面上的每个N + +区上形成具有固定深度的绝缘层。 绝缘层限制形成在N + +区域之间的电流路径区域。 N + +区域的侧面被绝缘层覆盖。 通过从绝缘层露出的底表面使N + +区与外延层接触。

公开(公告)号：US20080239817A1

公开(公告)日：2008-10-02

申请号：US12078446

申请日：2008-03-31

申请人： Mitsutaka Katada ,  Yukiaki Yogo ,  Akira Tai ,  Yukihiko Watanabe

发明人： Mitsutaka Katada ,  Yukiaki Yogo ,  Akira Tai ,  Yukihiko Watanabe

IPC分类号： G11C16/10

CPC分类号： H01L29/4983 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate having a source, a drain, and a channel region between the source and the drain. The channel region has a first end portion near the drain, a second end portion near the source, and a middle portion between the first and second end portions. The first and second end portions having approximately same width. The memory device is electrically erased by using a hot carrier generated in the first end portion due to avalanche breakdown. The channel region includes a first channel extending from the drain and a second channel adjacent to the first channel. An impurity concentration of the second channel is higher than that of the first channel. An interface between the first and second channels is located in the middle portion between the first and second end portions.

摘要翻译： 非易失性半导体存储器件包括在源极和漏极之间具有源极，漏极和沟道区域的半导体衬底。 沟道区域具有靠近漏极的第一端部，靠近源极的第二端部，以及第一和第二端部之间的中间部分。 第一和第二端部具有大致相同的宽度。 通过使用由于雪崩击穿而在第一端部中产生的热载体来电存储器件。 沟道区域包括从漏极延伸的第一通道和邻近第一通道的第二通道。 第二通道的杂质浓度高于第一通道的杂质浓度。 第一和第二通道之间的界面位于第一和第二端部之间的中间部分。

公开(公告)号：US07796442B2

公开(公告)日：2010-09-14

申请号：US12078446

申请日：2008-03-31

申请人： Mitsutaka Katada ,  Yukiaki Yogo ,  Akira Tai ,  Yukihiko Watanabe

发明人： Mitsutaka Katada ,  Yukiaki Yogo ,  Akira Tai ,  Yukihiko Watanabe

IPC分类号： G11C16/04

CPC分类号： H01L29/4983 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate having a source, a drain, and a channel region between the source and the drain. The channel region has a first end portion near the drain, a second end portion near the source, and a middle portion between the first and second end portions. The first and second end portions having approximately same width. The memory device is electrically erased by using a hot carrier generated in the first end portion due to avalanche breakdown. The channel region includes a first channel extending from the drain and a second channel adjacent to the first channel. An impurity concentration of the second channel is higher than that of the first channel. An interface between the first and second channels is located in the middle portion between the first and second end portions.

摘要翻译： 非易失性半导体存储器件包括在源极和漏极之间具有源极，漏极和沟道区域的半导体衬底。 沟道区域具有靠近漏极的第一端部，靠近源极的第二端部，以及第一和第二端部之间的中间部分。 第一和第二端部具有大致相同的宽度。 通过使用由于雪崩击穿而在第一端部中产生的热载体来电存储器件。 沟道区域包括从漏极延伸的第一通道和邻近第一通道的第二通道。 第二通道的杂质浓度高于第一通道的杂质浓度。 第一和第二通道之间的界面位于第一和第二端部之间的中间部分。