公开(公告)号：US06537884B1

公开(公告)日：2003-03-25

申请号：US09389381

申请日：1999-09-03

申请人： Yukiaki Yogo ,  Shigemitsu Fukatsu

发明人： Yukiaki Yogo ,  Shigemitsu Fukatsu

IPC分类号： H01L21336

CPC分类号： H01L29/66659 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665

摘要： A semiconductor device having an offset-gate structure, which can achieve a release of an electric field concentration and a lowering a transistor resistance at the same time. A semiconductor device has the offset-gate structure in which an offset region, at which a gate portion is not formed, is formed between an end of the gate portion and a drain on a silicon substrate. Surfaces of a source, the drain and a gate electrode of the gate portion are silicides to reduce a transistor resistance. Whereas a surface of the offset region formed between the gate portion and the drain does not include silicide. to prevent a potential of an end portion of the gate portion from being identical to a potential of the drain due to silicide. Therefore, it can achieve a release of an electric field concentration and a lowering a transistor resistance at the same time.

摘要翻译： 具有偏移栅极结构的半导体器件可同时实现电场浓度的释放和降低晶体管电阻。 半导体器件具有偏移栅结构，其中在栅极部分的端部和硅衬底上的漏极之间形成有未形成栅极部分的偏移区域。 栅极部分的源极，漏极和栅电极的表面是硅化物，以减小晶体管电阻。 而形成在栅极部分和漏极之间的偏移区域的表面不包括硅化物。 以防止栅极部分的端部的电位与由硅化物引起的漏极的电位相同。 因此，能够同时实现电场浓度的释放和晶体管电阻的降低。

公开(公告)号：US5986302A

公开(公告)日：1999-11-16

申请号：US18305

申请日：1998-02-03

申请人： Shigemitsu Fukatsu ,  Tsutomu Kawaguchi ,  Takuya Okuno ,  Yukiaki Yogo

发明人： Shigemitsu Fukatsu ,  Tsutomu Kawaguchi ,  Takuya Okuno ,  Yukiaki Yogo

IPC分类号： H01L21/28 ,  H01L29/788 ,  H01L29/76 ,  H01L29/792

CPC分类号： H01L21/28273 ,  H01L29/7885

摘要： A floating gate of a semiconductor memory device has a gate bird beak on an end portion thereof. Further, a positional relationship between the floating gate and a drain is controlled such that a depletion layer formed within the drain in a non-selected state of the semiconductor memory device faces the gate bird beak without interposing the drain therebetween. Accordingly, drain disturbance can be efficiently prevented.

摘要翻译： 半导体存储器件的浮置栅极在其端部具有栅极鸟嘴。 此外，控制浮置栅极和漏极之间的位置关系，使得形成在半导体存储器件的未选择状态的漏极内的耗尽层面对栅极鸟嘴而不在其间插入漏极。 因此，能够有效地防止漏极干扰。

公开(公告)号：US5830771A

公开(公告)日：1998-11-03

申请号：US525143

申请日：1995-09-08

申请人： Shigemitsu Fukatsu ,  Ryouichi Kubokoya ,  Akira Kuroyanagi

发明人： Shigemitsu Fukatsu ,  Ryouichi Kubokoya ,  Akira Kuroyanagi

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

CPC分类号： H01L21/28273

摘要： The insulating ability of a semiconductor device of two-layer gate electrode structure, such as EPROM, is improved at the upper surface of the first gate electrode as well as at the upper and lower edge parts of the first gate electrode. A LOCOS film is formed on a semiconductor substrate, and a floating gate is formed by patterning. Next, the first oxide film is formed on the floating gate, and then the first oxide film is etched out. Subsequently, the second oxide film is formed on the floating gate, and a control gate is formed on the floating gate using the second oxide film as an inter-layer insulating film. As a result of these two oxidations of the first and second oxide films and the removal of the first oxide film, the asperity of the upper surface of the floating gate is removed, and the upper and lower edge parts thereof are shaped into a round form.

摘要翻译： 在第一栅电极的上表面以及第一栅电极的上边缘部分和下边缘部分，改善了诸如EPROM的双层栅电极结构的半导体器件的绝缘能力。 在半导体衬底上形成LOCOS膜，通过图案化形成浮栅。 接着，在浮栅上形成第一氧化膜，然后蚀刻第一氧化膜。 接着，在浮置栅极上形成第二氧化物膜，使用第二氧化膜作为层间绝缘膜，在浮栅上形成控制栅极。 由于第一氧化膜和第二氧化物膜的两次氧化和第一氧化物膜的去除，浮栅的上表面的粗糙度被去除，其上边缘部分和下边缘部分被成形为圆形 。

公开(公告)号：US08659065B2

公开(公告)日：2014-02-25

申请号：US13225648

申请日：2011-09-06

申请人： Masakiyo Sumitomo ,  Yasushi Higuchi ,  Shigemitsu Fukatsu

发明人： Masakiyo Sumitomo ,  Yasushi Higuchi ,  Shigemitsu Fukatsu

IPC分类号： H01L27/108

CPC分类号： H01L29/7397 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66348

摘要： A semiconductor device includes a drift layer, a base layer on the drift layer, and trench gate structures. Each trench gate structure includes a trench reaching the drift layer by penetrating the base layer, a gate insulation layer on a wall surface of the trench, and a gate electrode on the gate insulation layer. A bottom portion of the trench gate structure is located in the drift layer and expands in a predetermined direction so that a distance between the bottom portions of adjacent trench gate structures is less than a distance between opening portions of adjacent trench gate structures in the direction. A thickness of the gate insulation layer is greater in the bottom portion than in the opening portion.

摘要翻译： 半导体器件包括漂移层，漂移层上的基极层和沟槽栅极结构。 每个沟槽栅极结构包括通过穿透基底层到达漂移层的沟槽，在沟槽的壁表面上的栅极绝缘层和栅极绝缘层上的栅极电极。 沟槽栅极结构的底部位于漂移层中并沿预定方向膨胀，使得相邻沟槽栅极结构的底部之间的距离小于相邻沟槽栅极结构在该方向上的开口部分之间的距离。 栅极绝缘层的厚度在底部比在开口部分大。

公开(公告)号：US5877531A

公开(公告)日：1999-03-02

申请号：US76737

申请日：1998-05-13

申请人： Shigemitsu Fukatsu ,  Ryoichi Kubokoya ,  Kenji Shiratori ,  Nobuyuki Ooya

发明人： Shigemitsu Fukatsu ,  Ryoichi Kubokoya ,  Kenji Shiratori ,  Nobuyuki Ooya

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L21/823807 ,  H01L27/0922 ,  Y10S438/919

摘要： A P-type impurity is doped by oblique ion implantation into N-type impurity diffusion layers formed respectively on both sides of a gate electrode of a Pch MOS transistor, thereby canceling the impurity of at least a portion of an N-type region overlapped by the gate electrode, to thereby suppress a rise in the threshold voltage of the P-channel type MIS transistor due to the N-type impurity diffusion layer and suppress fluctuations in the amount of current that can be made to flow and the current-driving capacity.

摘要翻译： 通过倾斜离子注入将P型杂质掺杂到分别形成在Pch MOS晶体管的栅电极的两侧上的N型杂质扩散层中，从而抵消与N型区域重叠的至少一部分N型区域的杂质 从而抑制由于N型杂质扩散层引起的P沟道型MIS晶体管的阈值电压的上升，并且抑制可流动的电流量的波动和电流驱动能力 。

公开(公告)号：US09178050B2

公开(公告)日：2015-11-03

申请号：US14347077

申请日：2012-09-13

申请人： Yasushi Higuchi ,  Shigemitsu Fukatsu ,  Masakiyo Sumitomo

发明人： Yasushi Higuchi ,  Shigemitsu Fukatsu ,  Masakiyo Sumitomo

IPC分类号： H01L29/66 ,  H01L29/739 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10

CPC分类号： H01L29/7397 ,  H01L29/0834 ,  H01L29/0843 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66348

摘要： In a semiconductor device, a trench gate has a bottom portion in a drift layer and a communication portion extending from a surface of a base layer to communicate with the bottom portion. A distance between adjacent bottom portions is smaller than a distance between adjacent communication portions in a x-direction. A region between adjacent trench gates is divided in a y-direction into an effective region as an electron injection source and an ineffective region which does not serve as the electron injection source. An interval L1 (>0) of the ineffective region in the y-direction, a length D1 of the communication portion in the z-direction, and a length D2 of the bottom portion in the z-direction satisfy L1≦2(D1+D2). The z-direction is orthogonal to a x-y plane defined by the x-direction and the y-direction which are orthogonal to each other.

摘要翻译： 在半导体器件中，沟槽栅极具有漂移层中的底部部分和从基底层的表面延伸以与底部部分连通的连通部分。 相邻底部之间的距离小于x方向上的相邻连通部之间的距离。 相邻沟槽栅极之间的区域在y方向上分成有效区域作为电子注入源和不用作电子注入源的无效区域。 y方向无效区域的间隔L1（> 0），z方向上的连通部的长度D1和z方向的底部的长度D2满足L1＆nlE; 2（D1 + D2）。 z方向与由x方向和y方向相互正交的x-y平面正交。

公开(公告)号：US20120056241A1

公开(公告)日：2012-03-08

申请号：US13225648

申请日：2011-09-06

申请人： Masakiyo SUMITOMO ,  Yasushi Higuchi ,  Shigemitsu Fukatsu

发明人： Masakiyo SUMITOMO ,  Yasushi Higuchi ,  Shigemitsu Fukatsu

IPC分类号： H01L29/739 ,  H01L21/331 ,  H01L21/28

CPC分类号： H01L29/7397 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66348

摘要： A semiconductor device includes a drift layer, a base layer on the drift layer, and trench gate structures. Each trench gate structure includes a trench reaching the drift layer by penetrating the base layer, a gate insulation layer on a wall surface of the trench, and a gate electrode on the gate insulation layer. A bottom portion of the trench gate structure is located in the drift layer and expands in a predetermined direction so that a distance between the bottom portions of adjacent trench gate structures is less than a distance between opening portions of adjacent trench gate structures in the direction. A thickness of the gate insulation layer is greater in the bottom portion than in the opening portion.

摘要翻译： 半导体器件包括漂移层，漂移层上的基极层和沟槽栅极结构。 每个沟槽栅极结构包括通过穿透基底层到达漂移层的沟槽，在沟槽的壁表面上的栅极绝缘层和栅极绝缘层上的栅极电极。 沟槽栅极结构的底部位于漂移层中并沿预定方向膨胀，使得相邻沟槽栅极结构的底部之间的距离小于相邻沟槽栅极结构在该方向上的开口部分之间的距离。 栅极绝缘层的厚度在底部比在开口部分大。

公开(公告)号：US06339557B1

公开(公告)日：2002-01-15

申请号：US09583868

申请日：2000-05-31

申请人： Tsutomu Kawaguchi ,  Shigemitsu Fukatsu ,  Mitsutaka Katada

发明人： Tsutomu Kawaguchi ,  Shigemitsu Fukatsu ,  Mitsutaka Katada

IPC分类号： G11C704

CPC分类号： G11C29/50004 ,  G11C16/04 ,  G11C29/50 ,  G11C29/50016

摘要： In a nonvolatile semiconductor memory, a floating gate electrode is disposed above a silicon substrate between source and drain regions, through a tunnel film, and a control gate electrode is disposed above the floating gate electrode through an insulating film. The substrate is grounded and at least two negative voltages are respectively applied to the control gate electrode, so that a voltage is applied to the tunnel film. In these cases, charge retention properties are evaluated. The voltages applied to the control gate electrode are controlled so that the voltage applied to the tunnel film does not exceed a voltage applied to the tunnel film during a memory operation. A charge retention property when no voltage is applied across the control gate electrode and the substrate, i.e., when no voltage is externally applied to the tunnel film, is estimated by the charge retention properties when the two voltages are applied to the control gate electrode.

摘要翻译： 在非易失性半导体存储器中，浮栅电极通过隧道膜设置在源极和漏极区域之间的硅衬底之上，并且控制栅电极通过绝缘膜设置在浮栅上。 衬底接地，并且至少两个负电压分别施加到控制栅电极，使得电压施加到隧道膜。 在这些情况下，评估电荷保留性能。 控制施加到控制栅电极的电压，使得施加到隧道膜的电压在存储操作期间不超过施加到隧道膜的电压。 当控制栅电极和基板两端施加电压时，即当没有施加电压到隧道膜时，电荷保持性能通过电荷保持特性来估计，当两个电压施加到控制栅电极时。

公开(公告)号：US5834347A

公开(公告)日：1998-11-10

申请号：US961086

申请日：1997-10-30

申请人： Shigemitsu Fukatsu ,  Ryoichi Kubokoya ,  Kenji Shiratori ,  Nobuyuki Ooya

发明人： Shigemitsu Fukatsu ,  Ryoichi Kubokoya ,  Kenji Shiratori ,  Nobuyuki Ooya

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/823807 ,  H01L27/0922 ,  Y10S438/919

摘要： A P-type impurity is doped by oblique ion implantation into N-type impurity diffusion layers formed respectively on both sides of a gate electrode of a Pch MOS transistor, thereby canceling the impurity of at least a portion of an N-type region overlapped by the gate electrode, to thereby suppress a rise in the threshold voltage of the P-channel type MIS transistor due to the N-type impurity diffusion layer and suppress fluctuations in the amount of current that can be made to flow and the current-driving capacity.

公开(公告)号：US20140217464A1

公开(公告)日：2014-08-07

申请号：US14347077

申请日：2012-09-13

申请人： Yasushi Higuchi ,  Shigemitsu Fukatsu ,  Masakiyo Sumitomo

发明人： Yasushi Higuchi ,  Shigemitsu Fukatsu ,  Masakiyo Sumitomo

IPC分类号： H01L29/739 ,  H01L29/423

CPC分类号： H01L29/7397 ,  H01L29/0834 ,  H01L29/0843 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66348

摘要： In a semiconductor device, a trench gate has a bottom portion in a drift layer and a communication portion extending from a surface of a base layer to communicate with the bottom portion. A distance between adjacent bottom portions is smaller than a distance between adjacent communication portions in a x-direction. A region between adjacent trench gates is divided in a y-direction into an effective region as an electron injection source and an ineffective region which does not serve as the electron injection source. An interval L1 (>0) of the ineffective region in the y-direction, a length D1 of the communication portion in the z-direction, and a length D2 of the bottom portion in the z-direction satisfy L1≦2(D1+D2). The z-direction is orthogonal to a x-y plane defined by the x-direction and the y-direction which are orthogonal to each other.

摘要翻译： 在半导体器件中，沟槽栅极具有漂移层中的底部部分和从基底层的表面延伸以与底部部分连通的连通部分。 相邻底部之间的距离小于x方向上的相邻连通部之间的距离。 相邻沟槽栅极之间的区域在y方向上分成有效区域作为电子注入源和不用作电子注入源的无效区域。 y方向无效区域的间隔L1（> 0），z方向的连通部的长度D1和z方向的底部的长度D2满足L1＆nlE; 2（D1 + D2）。 z方向与由x方向和y方向相互正交的x-y平面正交。