公开(公告)号：US5969998A

公开(公告)日：1999-10-19

申请号：US213773

申请日：1998-12-17

申请人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

发明人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00 ,  G11C11/24

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C7/065

摘要： A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode coupled to a word line and being connected between the capacitor and a bit line. Sense amplifier circuits are connected to the bit line pairs, and have a first and a second common source line. A decoder and a word line driver are connected to the word lines. A MOS transistor is connected between the power supply voltage and the first common source line, for selectively supplying it with a first voltage which potentially defines a high-level voltage for the bit line pairs. A voltage generator is connected through a MOS transistor to the second common source line, for generating a second voltage which potentially defines a low-level voltage for the bit line pairs, and which is selectively supplied to the second common source line. The second voltage is greater in potential than the ground potential, which is employed as a source voltage.

公开(公告)号：US5299154A

公开(公告)日：1994-03-29

申请号：US907645

申请日：1992-07-02

申请人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

发明人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C11/24

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C7/065

摘要： A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode coupled to a word line and being connected between the capacitor and a bit line. Sense amplifier circuits are connected to the bit line pairs, and have a first and a second common source line. A decoder and a word line driver are connected to the word lines. A MOS transistor is connected between the power supply voltage and the first common source line, for selectively supplying it with a first voltage which potentially defines a high-level voltage for the bit line pairs. A voltage generator is connected through a MOS transistor to the second common source line, for generating a second voltage which potentially defines a low-level voltage for the bit line pairs, and which is selectively supplied to the second common source line. The second voltage is greater in potential than the ground potential, which is employed as a source voltage.

摘要翻译： MOS动态随机存取存储器包括多对位线和横向于位线的字线以定义交叉点，存储器单元阵列布置在该交叉点处。 每个单元具有存储电容器和传输门MOS晶体管，其具有耦合到字线并连接在电容器和位线之间的栅电极。 感测放大器电路连接到位线对，并且具有第一和第二公共源极线。 解码器和字线驱动器连接到字线。 MOS晶体管连接在电源电压和第一公共源极线之间，用于选择性地向其提供潜在地限定位线对的高电平电压的第一电压。 电压发生器通过MOS晶体管连接到第二公共源极线，用于产生可能限定位线对的低电平电压的第二电压，并且被选择性地提供给第二公共源极线。 第二电压的电位比接地电位大，用作电源电压。

公开(公告)号：US5638329A

公开(公告)日：1997-06-10

申请号：US420079

申请日：1995-04-11

申请人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

发明人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C7/065

摘要： A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode coupled to a word line and being connected between the capacitor and a bit line. Sense amplifier circuits are connected to the bit line pairs, and have a first and a second common source line. A decoder and a word line driver are connected to the word lines. AMOS transistor is connected between the power supply voltage and the first common source line, for selectively supplying it with a first voltage which potentially defines a high-level voltage for the bit line pairs. A voltage generator is connected through a MOS transistor to the second common source line, for generating a second voltage which potentially defines a low-level voltage for the bit line pairs, and which is selectively supplied to the second common source line. The second voltage is greater in potential than the ground potential, which is employed as a source voltage.

摘要翻译： MOS动态随机存取存储器包括多对位线和横向于位线的字线以定义交叉点，存储器单元阵列布置在该交叉点处。 每个单元具有存储电容器和传输门MOS晶体管，其具有耦合到字线并连接在电容器和位线之间的栅电极。 感测放大器电路连接到位线对，并且具有第一和第二公共源极线。 解码器和字线驱动器连接到字线。 AMOS晶体管连接在电源电压和第一公共源极线之间，用于选择性地向其提供潜在地限定位线对的高电平电压的第一电压。 电压发生器通过MOS晶体管连接到第二公共源极线，用于产生可能限定位线对的低电平电压的第二电压，并且被选择性地提供给第二公共源极线。 第二电压的电位比接地电位大，用作电源电压。

公开(公告)号：US5426604A

公开(公告)日：1995-06-20

申请号：US197409

申请日：1994-02-16

申请人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

发明人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C11/24

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C7/065

摘要： A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode coupled to a word line and being connected between the capacitor and a bit line. Sense amplifier circuits are connected to the bit line pairs, and have a first and a second common source line. A decoder and a word line driver are connected to the word lines. A MOS transistor is connected between the power supply voltage and the first common source line, for selectively supplying it with a first voltage which potentially defines a high-level voltage for the bit line pairs. A voltage generator is connected through a MOS transistor to the second common source line, for generating a second voltage which potentially defines a low-level voltage for the bit line pairs, and which is selectively supplied to the second common source line. The second voltage is greater in potential than the ground potential, which is employed as a source voltage.

摘要翻译： MOS动态随机存取存储器包括多对位线和横向于位线的字线以定义交叉点，存储器单元阵列布置在该交叉点处。 每个单元具有存储电容器和传输门MOS晶体管，其具有耦合到字线并连接在电容器和位线之间的栅电极。 感测放大器电路连接到位线对，并且具有第一和第二公共源极线。 解码器和字线驱动器连接到字线。 MOS晶体管连接在电源电压和第一公共源极线之间，用于选择性地向其提供潜在地限定位线对的高电平电压的第一电压。 电压发生器通过MOS晶体管连接到第二公共源极线，用于产生可能限定位线对的低电平电压的第二电压，并且被选择性地提供给第二公共源极线。 第二电压的电位比接地电位大，用作电源电压。

公开(公告)号：US5870339A

公开(公告)日：1999-02-09

申请号：US742924

申请日：1996-11-01

申请人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

发明人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C16/04

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C7/065

摘要： A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode coupled to a word line and being connected between the capacitor and a bit line. Sense amplifier circuits are connected to the bit line pairs, and have a first and a second common source line. A decoder and a word line driver are connected to the word lines. A MOS transistor is connected between the power supply voltage and the first common source line, for selectively supplying it with a first voltage which potentially defines a high-level voltage for the bit line pairs. A voltage generator is connected through a MOS transistor to the second common source line, for generating a second voltage which potentially defines a low-level voltage for the bit line pairs, and which is selectively supplied to the second common source line. The second voltage is greater in potential than the ground potential, which is employed as a source voltage.

公开(公告)号：US06993691B2

公开(公告)日：2006-01-31

申请号：US10120146

申请日：2002-04-11

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Yukihito Oowaki ,  Katsuhiko Hoya ,  Takeshi Watanabe

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Yukihito Oowaki ,  Katsuhiko Hoya ,  Takeshi Watanabe

IPC分类号： G11C29/00

CPC分类号： G11C8/08 ,  G11C11/22

摘要： Potential of a word line connected to any selected one of memory cells is lowered and potential of word lines connected to non-selected memory cells are raised. The potential of the plate line is raised and lowered. The potential of the bit line is raised and lowered. After this, reading data from the memory cells after potential raising and lowering of the plate line and potential raising and lowering of the bit line have been alternately performed at least one time, thereby to determine attenuation of polarization in the ferroelectric capacitor.

公开(公告)号：US07057917B2

公开(公告)日：2006-06-06

申请号：US10743906

申请日：2003-12-24

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

摘要翻译： 链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线 通过开关晶体管，放大该位线及其互补位线的电压的读出放大器，以及插在开关晶体管和读出放大器之间的晶体管。 作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值 电压和比较放大。 利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

公开(公告)号：US5838038A

公开(公告)日：1998-11-17

申请号：US478620

申请日：1995-06-07

申请人： Daisaburo Takashima ,  Shigeyoshi Watanabe ,  Tohru Ozaki ,  Takeshi Hamamoto ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Shigeyoshi Watanabe ,  Tohru Ozaki ,  Takeshi Hamamoto ,  Yukihito Oowaki

IPC分类号： G11C7/18 ,  H01L27/108

CPC分类号： G11C7/18 ,  G11C2211/4013

摘要： A semiconductor memory device includes active regions arranged on a semiconductor substrate such that those of the active regions which are adjacent in the word line direction deviate in the bit line direction, MOS transistors respectively formed in the active regions and each having a source and a drain one of which is connected to the bit line, a plurality of trenches each arranged to another set of source an drain regions and arranged to deviate in the word line direction in the respective active regions, those of the trenches which are adjacent with a through word line disposed therebetween being arranged to deviate in the bit line direction so as to be set closer to each other, a plurality of storage electrodes respectively formed in the trenches with capacitor insulative films disposed therebetween, and connection electrodes arranged between the word lines and each connecting the other of the source and drain to the storage electrode.

摘要翻译： 半导体存储器件包括布置在半导体衬底上的有源区域，使得在字线方向上相邻的有源区域在位线方向偏离的有源区域分别形成在有源区域中并且各自具有源极和漏极 其中一个连接到位线，多个沟槽，每个沟槽被布置成另一组源极漏极区域，并且被布置成在相应的有源区域中的字线方向偏离，与通过字相邻的沟槽的那些沟槽 配置在它们之间的线被布置为在位线方向上偏离以使得彼此更靠近，分别形成在沟槽中的多个存储电极，其中设置有电容器绝缘膜，以及布置在字线和每个连接之间的连接电极 另一个源极和漏极到存储电极。

公开(公告)号：US5499209A

公开(公告)日：1996-03-12

申请号：US457738

申请日：1995-06-01

申请人： Yukihito Oowaki ,  Daisaburo Takashima ,  Masako Ohta

发明人： Yukihito Oowaki ,  Daisaburo Takashima ,  Masako Ohta

IPC分类号： G11C11/407 ,  G11C11/408 ,  G11C7/00 ,  H03K17/687

CPC分类号： G11C11/4085

摘要： A word-line drive voltage generation circuit for use in a dynamic random-access memory is disclosed which is connected to a word line via a row decoder including MOS transistors. The circuit includes a charge-bootstrap capacitor having insulated electrodes, one of which is connected to a first reference voltage generator via a switching MOS transistor, and the other of which is connected via a MOS transistor to a second reference voltage generator. These voltage generators provide the capacitor with the constant d.c. voltage that are essentially insensitive to variation in the power supply voltage for the memory. The resultant word-line drive voltage may thus be free from variation in the power supply voltage during the operation modes of the memory. This enables the word-line voltage to be high enough to allow successful "H" level writing at a selected memory cell without creation of any unwantedly increased dielectric breakdown therein, in the entire allowable range of the power supply voltage.

摘要翻译： 公开了一种用于动态随机存取存储器的字线驱动电压产生电路，其通过包括MOS晶体管的行解码器连接到字线。 该电路包括具有绝缘电极的电荷自举电容器，其中一个经由开关MOS晶体管连接到第一参考电压发生器，另一个经由MOS晶体管连接到第二参考电压发生器。 这些电压发生器为电容器提供恒定的直流电压。 对于存储器的电源电压的变化基本上不敏感的电压。 因此，在存储器的操作模式期间，所得到的字线驱动电压可能没有电源电压的变化。 这使得字线电压足够高，以允许在所选择的存储器单元中成功地“H”电平写入，而不会在电源电压的整个允许范围内产生不必要的增加的电介质击穿。

公开(公告)号：US5084842A

公开(公告)日：1992-01-28

申请号：US536718

申请日：1990-06-12

申请人： Kenji Tsuchida ,  Yukihito Oowaki ,  Daisaburo Takashima

发明人： Kenji Tsuchida ,  Yukihito Oowaki ,  Daisaburo Takashima

IPC分类号： G11C11/409 ,  G11C11/401 ,  G11C11/4091 ,  G11C11/4094 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10805 ,  G11C11/4091 ,  G11C11/4094

摘要： A dynamic random access memory has a substrate, plural pairs of parallel bit lines provided on the substrate, parallel word lines insulatively crossing the parallel bit lines to define cross points therebetween, and memory cells provided at the cross points. Each memory cell has a data storage capacitor and a transistor. Sense amplifiers are provided at bit line pairs, respectively, to sense a data voltage. A discharge control section, which is associated with the sense amplifiers, forms discharge paths branched between the bit line pairs and the substrate grounded to progress the discharging of charges, when a certain word line is designated and a memory cell is selected from those memory cells which are connected to the certain word line, whereby the operational speed of the memory is increased.

摘要翻译： 动态随机存取存储器具有衬底，设置在衬底上的多对并行位线，并行字线绝对地穿过并行位线以限定它们之间的交叉点，以及设置在交叉点处的存储单元。 每个存储单元具有数据存储电容器和晶体管。 分别在位线对处提供感测放大器以感测数据电压。 与读出放大器相关联的放电控制部分在指定某个字线并且从那些存储器单元中选择存储器单元时，形成在位线对和衬底之间分支的放电路径，从而导致电荷的放电 其连接到某个字线，由此增加存储器的操作速度。