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125 条记录 (耗时 0.027 秒)

    Data sensing arrangement using first and second bit lines
    1.
    发明授权
    Data sensing arrangement using first and second bit lines 有权
    使用第一和第二位线的数据传感装置

    公开(公告)号：US08264900B2

    公开(公告)日：2012-09-11

    申请号：US13300141

    申请日：2011-11-18

    申请人： Yung-Feng Lin ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    发明人： Yung-Feng Lin ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1048 ,  G11C16/28

    摘要： Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers.

    摘要翻译： 通过使用扭曲的数据线和差分感测放大器来减轻耦合到相邻数据线的非易失性存储器中的数据线上的过度擦除感应噪声。 耦合到数据线中的噪声由耦合到参考数据线中的相似噪声补偿并在差分感测放大器中被消除。

    DATA SENSING ARRANGEMENT USING FIRST AND SECOND BIT LINES
    2.
    发明申请
    DATA SENSING ARRANGEMENT USING FIRST AND SECOND BIT LINES 有权
    使用第一和第二位线的数据传感装置

    公开(公告)号：US20120063228A1

    公开(公告)日：2012-03-15

    申请号：US13300141

    申请日：2011-11-18

    申请人： YUNG-FENG LIN ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    发明人： YUNG-FENG LIN ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC分类号： G11C16/26

    CPC分类号： G11C7/1048 ,  G11C16/28

    摘要： Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers.

    摘要翻译： 通过使用扭曲的数据线和差分感测放大器来减轻耦合到相邻数据线的非易失性存储器中的数据线上的过度擦除感应噪声。 耦合到数据线中的噪声由耦合到参考数据线中的相似噪声补偿并在差分感测放大器中被消除。

    Memory and method for charging a word line thereof
    3.
    发明授权
    Memory and method for charging a word line thereof 有权

    公开(公告)号：US08411509B2

    公开(公告)日：2013-04-02

    申请号：US11976975

    申请日：2007-10-30

    申请人： Chun-Yi Lee ,  Yung-Feng Lin ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    发明人： Chun-Yi Lee ,  Yung-Feng Lin ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC分类号： G11C11/34

    CPC分类号： G11C8/08 ,  G11C8/14 ,  G11C16/08

    摘要： A memory and method for charging a word line thereof are disclosed. The memory includes a first word line driver, a first word line and a first switch. The first word line driver is connected to a first operational voltage for receiving a first control signal. The first word line comprises a start terminal connected to an output terminal of the first word line driver. The first switch is connected to a second operational voltage and an end terminal of the first word line. The second operational voltage is not smaller than the first operational voltage. When the first word line driver is controlled by the first control signal to start charging up the first word line, the first switch is simultaneously turned on to provide another charging path for the first word line until the first word line is charged to the first operational voltage.

    Memory and method for charging a word line thereof
    5.
    发明申请
    Memory and method for charging a word line thereof 有权
    用于对其字线进行充电的存储器和方法

    公开(公告)号：US20090116293A1

    公开(公告)日：2009-05-07

    申请号：US11976975

    申请日：2007-10-30

    申请人： Chun-Yi Lee ,  Yung-Feng Lin ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    发明人： Chun-Yi Lee ,  Yung-Feng Lin ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC分类号： G11C16/06 ,  G11C8/08 ,  G11C5/02

    CPC分类号： G11C8/08 ,  G11C8/14 ,  G11C16/08

    摘要： A memory and method for charging a word line thereof are disclosed. The memory includes a first word line driver, a first word line and a first switch. The first word line driver is connected to a first operational voltage for receiving a first control signal. The first word line comprises a start terminal connected to an output terminal of the first word line driver. The first switch is connected to a second operational voltage and an end terminal of the first word line. The second operational voltage is not smaller than the first operational voltage. When the first word line driver is controlled by the first control signal to start charging up the first word line, the first switch is simultaneously turned on to provide another charging path for the first word line until the first word line is charged to the first operational voltage.

    摘要翻译： 公开了一种用于对其字线进行充电的存储器和方法。 存储器包括第一字线驱动器，第一字线和第一开关。 第一字线驱动器连接到用于接收第一控制信号的第一操作电压。 第一字线包括连接到第一字线驱动器的输出端的起始端。 第一开关连接到第一字线的第二工作电压和端子。 第二工作电压不小于第一工作电压。 当第一字线驱动器由第一控制信号控制以开始向第一字线充电时，第一开关同时导通，以为第一字线提供另一充电路径，直到第一字线被充电到第一操作 电压。

    Twisted data lines to avoid over-erase cell result coupling to normal cell result
    6.
    发明授权
    Twisted data lines to avoid over-erase cell result coupling to normal cell result 有权
    扭转的数据线，以避免过度擦除细胞结果与正常细胞结果的耦合

    公开(公告)号：US08085611B2

    公开(公告)日：2011-12-27

    申请号：US12545793

    申请日：2009-08-21

    申请人： Yung Feng Lin ,  Kuen-Long Chang ,  Chun Hsiung Hung

    发明人： Yung Feng Lin ,  Kuen-Long Chang ,  Chun Hsiung Hung

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1048 ,  G11C16/28

    摘要： Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers.

    摘要翻译： 通过使用扭曲的数据线和差分感测放大器来减轻耦合到相邻数据线的非易失性存储器中的数据线上的过度擦除感应噪声。 耦合到数据线中的噪声由耦合到参考数据线中的相似噪声补偿并在差分感测放大器中被消除。

    Method and apparatus for reducing erase disturb of memory by using recovery bias
    7.
    发明授权
    Method and apparatus for reducing erase disturb of memory by using recovery bias 有权
    通过使用恢复偏压来减少存储器的擦除干扰的方法和装置

    公开(公告)号：US08982640B2

    公开(公告)日：2015-03-17

    申请号：US13426985

    申请日：2012-03-22

    申请人： Chun Hsiung Hung ,  Bo-Chang Wu ,  Kuen-Long Chang ,  Ken-Hui Chen

    发明人： Chun Hsiung Hung ,  Bo-Chang Wu ,  Kuen-Long Chang ,  Ken-Hui Chen

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3431 ,  G11C16/14 ,  G11C16/3418 ,  G11C16/344

    摘要： A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.

    摘要翻译： 非易失性存储器阵列被分成多个存储器组。 非易失性存储器阵列接收擦除命令以擦除第一组存储器组，而不是第二组存储器组。 控制电路响应于擦除命令来擦除第一组存储器组，通过应用恢复偏压布置来调整第二组存储器组的至少一个存储器组中的存储器单元的阈值电压。 通过将恢复偏压装置应用于第二组存储器组的至少一个存储器组中的存储器单元，至少部分地在恢复偏压装置期间校正擦除干扰。

    Serial memory interface for extended address space
    9.
    发明授权
    Serial memory interface for extended address space 有权
    用于扩展地址空间的串行存储器接口

    公开(公告)号：US08677100B2

    公开(公告)日：2014-03-18

    申请号：US12813395

    申请日：2010-06-10

    申请人： Yulan Kuo ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    发明人： Yulan Kuo ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC分类号： G06F9/34

    CPC分类号： G06F9/30076 ,  G06F9/30189 ,  G06F9/342

    摘要： An integrated circuit memory device has a memory array and control logic with at least a first addressing mode in which the instruction includes a first instruction code and an address of a first length; and a second addressing mode in which the instruction includes the first instruction code and an address of a second length. The first length of the address is different from the second length of the address.

    摘要翻译： 集成电路存储器件具有存储器阵列和具有至少第一寻址模式的控制逻辑，其中指令包括第一指令代码和第一长度的地址; 以及第二寻址模式，其中指令包括第一指令代码和第二长度的地址。 地址的第一个长度与地址的第二个长度不同。

    MEMORY APPARATUS
    10.
    发明申请
    MEMORY APPARATUS 有权
    记忆装置

    公开(公告)号：US20130326184A1

    公开(公告)日：2013-12-05

    申请号：US13584393

    申请日：2012-08-13

    申请人： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo

    发明人： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo

    IPC分类号： G06F12/00

    CPC分类号： G11C7/1072 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/104

    摘要： A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.

    摘要翻译： 存储装置包括主机装置和从装置。 主机设备存储验证数据。 从设备包括存储器单元，控制单元和逻辑单元。 控制单元驱动存储单元以在数据传输子时段中提供存储数据，并且还在虚拟子周期中提供指示第一验证数据的控制信号。 逻辑单元响应于第一控制信号，在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。 前导码数据和存储数据根据内部时钟信号发送。 主机设备根据外部时钟信号对第一前同步码数据进行采样，并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。