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1.发明授权Active pixel sensor cell with integrating varactor and method for using such cell 有权具有积分变容二极管的有源像素传感器单元和使用这种单元的方法公开(公告)号：US07262401B2
公开(公告)日：2007-08-28
申请号：US11496951
申请日：2006-08-01
CPC分类号： H01L27/14609 , H04N5/35572 , H04N5/361 , H04N5/37452
摘要： An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.
摘要翻译： 包括至少一个光电二极管和复位电路的有源像素传感器单元和耦合到光电二极管的积分变容二极管，用于读出这样的单元的方法以及包括这种单元阵列的图像传感器。 在曝光间隔期间，可以将光电二极管暴露于光子，以在光电二极管的第一节点处累积次曝光电荷序列。 在曝光间隔的不同子曝光间隔期间，每个次曝光电荷在第一节点处累积。 在每个复位间隔的每一个期间复位光电二极管，每个复位间隔发生在不同的次曝光间隔之前。 指示在曝光间隔期间在存储节点处累积的曝光电荷的输出信号可以从单元断言，其中曝光电荷指示所有次曝光电荷的总和。
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2.发明授权Active pixel sensor cell with integrating varactor and method for using such cell 有权具有积分变容二极管的有源像素传感器单元和使用这种单元的方法公开(公告)号：US07102117B2
公开(公告)日：2006-09-05
申请号：US10863058
申请日：2004-06-08
IPC分类号： H01L27/00
CPC分类号： H01L27/14609 , H04N5/35572 , H04N5/361 , H04N5/37452
摘要： An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.
摘要翻译： 包括至少一个光电二极管和复位电路的有源像素传感器单元和耦合到光电二极管的积分变容二极管，用于读出这样的单元的方法以及包括这种单元阵列的图像传感器。 在曝光间隔期间，可以将光电二极管暴露于光子，以在光电二极管的第一节点处累积次曝光电荷序列。 在曝光间隔的不同子曝光间隔期间，每个次曝光电荷在第一节点处累积。 在每个复位间隔的每一个期间复位光电二极管，每个复位间隔发生在不同的次曝光间隔之前。 指示在曝光间隔期间在存储节点处累积的曝光电荷的输出信号可以从单元断言，其中曝光电荷指示所有次曝光电荷的总和。
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3.发明授权公开(公告)号：US07233521B1
公开(公告)日：2007-06-19
申请号：US11078761
申请日：2005-03-11
IPC分类号： G11C11/34
CPC分类号： G11C27/005 , G11C11/5621 , G11C16/0441 , G11C16/10
摘要： A storage device that is capable of receiving an analog signal and storing it as a digital signal. The storage device includes an input node configured to receive an analog input voltage and two non-volatile storage cells. A second non-volatile memory cell is coupled to receive the analog input signal from the input node. The second non-volatile memory cell is capable of being programmed to a one of a plurality of programming states. The first non-volatile memory cell, which is coupled to the second non-volatile memory cell, is also capable of being programmed to one of a plurality of programming states. During operation, the second non-volatile memory cell and the first non-volatile memory cell are both programmed to a selected second programming state indicative of the magnitude of the analog input voltage. The first programming state and the second programming state are together are indicative of a digital value commensurate with the magnitude of the analog input voltage.
摘要翻译： 一种能够接收模拟信号并将其存储为数字信号的存储装置。 存储装置包括被配置为接收模拟输入电压的输入节点和两个非易失性存储单元。 第二非易失性存储单元被耦合以从输入节点接收模拟输入信号。 第二非易失性存储单元能够被编程为多个编程状态之一。 耦合到第二非易失性存储单元的第一非易失性存储单元也能够被编程为多个编程状态之一。 在操作期间，第二非易失性存储器单元和第一非易失性存储器单元都被编程为指示模拟输入电压的大小的选择的第二编程状态。 第一编程状态和第二编程状态一起表示与模拟输入电压的大小相称的数字值。
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公开(公告)号：US07209503B1
公开(公告)日：2007-04-24
申请号：US10838671
申请日：2004-05-03
IPC分类号： H01S5/00
CPC分类号： H01L27/1446 , H01L27/146
摘要： An integrated circuit is powered by exposing conductive regions, such as the p+ source regions of the PMOS transistors that are formed to receive a supply voltage, to light energy from a light source. The conductive regions function as photodiodes that produce voltages on the conductive regions via the photovoltaic effect.
摘要翻译： 集成电路通过将形成为接收电源电压的PMOS晶体管的p +源极区域等导电区域暴露于来自光源的光能来供电。 导电区域用作通过光电效应在导电区域上产生电压的光电二极管。
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公开(公告)号：US07113427B1
公开(公告)日：2006-09-26
申请号：US11076711
申请日：2005-03-09
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L29/7881
摘要： NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two parallel transistors having different threshold voltages, and another embodiment uses one transistor with variable doping. The gate current curve provides two programming zones. Programming the first state includes applying a voltage across a channel, ramping up a gate voltage in the first programming zone, followed by ramping it back down. Programming the second state comprises applying a voltage across a channel, ramping up a gate voltage past the first programming zone and into the second programming zone, followed by ramping it back down. Ramping the voltage back down may optionally be preceded by turning off the voltage across the channel.
摘要翻译： 用于存储三个电荷电平的NVM单元：一个擦除和两个编程状态。 该单元包括提供具有平坦区域或第二峰值的形状的栅极电流对栅极电压曲线的晶体管结构。 为了提供这样的结构，一个实施例组合了具有不同阈值电压的两个并联晶体管，另一实施例使用一个具有可变掺杂的晶体管 栅极电流曲线提供两个编程区域。 对第一状态进行编程包括在一个通道上施加电压，使第一个编程区中的栅极电压升高，然后将其向下斜坡。 对第二状态进行编程包括在通道上施加电压，将栅极电压升高到第一编程区并进入第二编程区，然后将其向下斜坡。 可以选择先将电压降低，然后关闭通道上的电压。
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公开(公告)号：US07180379B1
公开(公告)日：2007-02-20
申请号：US10838485
申请日：2004-05-03
IPC分类号： G01N21/00
CPC分类号： G06F1/105
摘要： A synchronous clock signal is generated in a large number of local clock circuits at the same time by exposing photoconductive regions in each local clock circuit to a pulsed light source that operates at a fixed frequency. The photoconductive regions generate photoconductive currents which are sufficient to cause a logic inverter to switch states.
摘要翻译： 通过将每个本地时钟电路中的光电导区域暴露于以固定频率工作的脉冲光源，同时在多个本地时钟电路中产生同步时钟信号。 光电导区产生足以导致逻辑逆变器切换状态的光电流。
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公开(公告)号：US07298653B1
公开(公告)日：2007-11-20
申请号：US10873872
申请日：2004-06-21
IPC分类号： G11C11/34
CPC分类号： G11C29/02 , G11C16/04 , G11C16/12 , G11C29/021 , G11C29/028 , G11C29/50004
摘要： In an EEPROM array the cells are pre-charged or pre-erased so that they will respond uniformly to the same read voltage level. By clearly defining the threshold voltage for the cells in their erased states and in their programmed states, it is possible to define more than one read voltage and thus provide cells that an store multiple values and even analog values.
摘要翻译： 在EEPROM阵列中，单元被预充电或预擦除，使得它们将均匀地响应于相同的读取电压电平。 通过明确定义其擦除状态和编程状态下的单元的阈值电压，可以定义多个读取电压，从而提供存储多个值和甚至模拟值的单元。
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8.发明授权Method and structure for addressing hot carrier degradation in high voltage devices 有权解决高压设备热载流子劣化的方法和结构公开(公告)号：US07180133B1
公开(公告)日：2007-02-20
申请号：US11016147
申请日：2004-12-17
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/0619 , H01L29/0634 , H01L29/086 , H01L29/0878 , H01L29/7835
摘要： In a method and structure for a high voltage LDMOS with reduced hot carrier degradation, the thick field oxide is eliminated and a reduced surface field achieved instead by including adjacent p+ and n+ regions in the drain well and shorting these regions to each other, or by including a p+ region in the drain well and biasing it to a positive voltage relative to the source voltage.
摘要翻译： 在具有减少的热载流子劣化的高电压LDMOS的方法和结构中，消除了厚场氧化物，并且通过在漏极阱中包括相邻的p +和n +区域而将这些区域彼此短路，或者通过 包括漏极阱中的p +区，并将其偏压到相对于源极电压的正电压。
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9.发明授权公开(公告)号：US08554529B2
公开(公告)日：2013-10-08
申请号：US11998478
申请日：2007-11-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of simulating an integrated circuit device under test (DUT) is provided, wherein the DUT includes a plurality of terminals. For each terminal of the DUT, a probe pulse is applied to the terminal and a reaction is recorded at the terminal and each of the other terminals to obtain values representative of reactive tails for the terminal. For each terminal, the values representative of the reactive tails obtained for the terminal are stored as an entry of a look-up table. Each entry includes n+x fields, wherein n represents a number of arguments in the entry and x represents a number of functions in the entry. For each terminal, a signal value at a selected time step is calculated.
摘要翻译： 提供了一种模拟被测集成电路器件（DUT）的方法，其中DUT包括多个端子。 对于DUT的每个端子，将探头脉冲施加到端子，并且在端子和每个其他端子处记录反应以获得表示端子的反应尾部的值。 对于每个终端，代表为终端获得的反应式尾部的值被存储为查找表的条目。 每个条目包括n + x个字段，其中n表示条目中的参数数，x表示条目中的一些函数。 对于每个终端，计算所选时间步长处的信号值。
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10.发明申请公开(公告)号：US20090144035A1
公开(公告)日：2009-06-04
申请号：US11998478
申请日：2007-11-30
IPC分类号： G06G7/48
CPC分类号： G06F17/5036
摘要： A modified “black box” integrated circuit simulation model is provided that is based only upon on the external steady-state and transient characteristics of a device under test (DUT). The method utilizes probe pulses as well as steady-state I-V and C-V look-up tables. In contrast to conventional black box simulation models, which support only steady-state and small signal frequency analysis, the disclosed method also supports large signal transient analysis.
摘要翻译： 提供了一种基于被测器件（DUT）的外部稳态和瞬态特性的改进的“黑匣子”集成电路仿真模型。 该方法利用探头脉冲以及稳态I-V和C-V查找表。 与仅支持稳态和小信号频率分析的常规黑盒仿真模型相反，所公开的方法还支持大信号瞬态分析。
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