公开(公告)号：US06717785B2

公开(公告)日：2004-04-06

申请号：US09819715

申请日：2001-03-29

申请人： Yutaka Fukuda ,  Ryoichi Okuda ,  Tomoatsu Makino ,  Kenji Yagi ,  Yukio Tsuzuki

发明人： Yutaka Fukuda ,  Ryoichi Okuda ,  Tomoatsu Makino ,  Kenji Yagi ,  Yukio Tsuzuki

IPC分类号： H02H308

CPC分类号： H03K17/0828 ,  H03K17/168

摘要： A semiconductor switching element driving circuit comprises an overcurrent limiting circuit which instantaneously drops a voltage of a gate terminal of an IGBT when a main IGBT current becomes larger than a predetermined level i1. An overcurrent protection circuit which first decreases the main IGBT current at a first inclination when the main IGBT current becomes larger than the other level i2 lower than the i1 and then reduces the main IGBT current at a steep second inclination when it becomes smaller than another level i3.

摘要翻译： 半导体开关元件驱动电路包括当主IGBT电流变得大于预定电平i1时瞬时降低IGBT的栅极端子的电压的过电流限制电路。 一个过电流保护电路，当主IGBT电流变得大于比i1低的另一个电平i2时，首先降低主IGBT电流，然后当其变得小于另一个电平时，以较陡峭的第二倾斜度降低主IGBT电流 i3。

公开(公告)号：US20090114947A1

公开(公告)日：2009-05-07

申请号：US12289852

申请日：2008-11-06

申请人： Yutaka Fukuda ,  Yukio Tsuzuki

发明人： Yutaka Fukuda ,  Yukio Tsuzuki

IPC分类号： H01L27/06 ,  G05F1/10

CPC分类号： H01L29/7397 ,  H01L27/0664 ,  H01L27/0694 ,  H01L2924/0002 ,  H03K2217/0027 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate, an insulated gate transistor formed to the semiconductor substrate, a diode formed to the semiconductor substrate, and a control transistor formed to the semiconductor substrate. A first current terminal of the insulated gate transistor is coupled to a cathode of the diode at a high potential side. A second current terminal of the insulated gate transistor is coupled to an anode of the diode at a low potential side. The control transistor is configured to turn off the insulated gate transistor by reducing a potential of a gate terminal of the insulated gate transistor when the diode conducts an electric current.

摘要翻译： 半导体器件包括半导体衬底，形成于半导体衬底的绝缘栅晶体管，形成于半导体衬底的二极管，和形成于半导体衬底的控制晶体管。 绝缘栅极晶体管的第一电流端子在高电位侧耦合到二极管的阴极。 绝缘栅晶体管的第二电流端子在低电位侧耦合到二极管的阳极。 控制晶体管被配置为当二极管导通电流时，通过减小绝缘栅极晶体管的栅极端子的电位来关断绝缘栅极晶体管。

公开(公告)号：US08125002B2

公开(公告)日：2012-02-28

申请号：US12289852

申请日：2008-11-06

申请人： Yutaka Fukuda ,  Yukio Tsuzuki

发明人： Yutaka Fukuda ,  Yukio Tsuzuki

IPC分类号： H01L29/43 ,  H01L29/45

CPC分类号： H01L29/7397 ,  H01L27/0664 ,  H01L27/0694 ,  H01L2924/0002 ,  H03K2217/0027 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate, an insulated gate transistor formed to the semiconductor substrate, a diode formed to the semiconductor substrate, and a control transistor formed to the semiconductor substrate. A first current terminal of the insulated gate transistor is coupled to a cathode of the diode at a high potential side. A second current terminal of the insulated gate transistor is coupled to an anode of the diode at a low potential side. The control transistor is configured to turn off the insulated gate transistor by reducing a potential of a gate terminal of the insulated gate transistor when the diode conducts an electric current.

摘要翻译： 半导体器件包括半导体衬底，形成于半导体衬底的绝缘栅晶体管，形成于半导体衬底的二极管，和形成于半导体衬底的控制晶体管。 绝缘栅极晶体管的第一电流端子在高电位侧耦合到二极管的阴极。 绝缘栅晶体管的第二电流端子在低电位侧耦合到二极管的阳极。 控制晶体管被配置为当二极管导通电流时，通过减小绝缘栅极晶体管的栅极端子的电位来关断绝缘栅极晶体管。

公开(公告)号：US08102025B2

公开(公告)日：2012-01-24

申请号：US11709272

申请日：2007-02-22

申请人： Yoshihiko Ozeki ,  Norihito Tokura ,  Yukio Tsuzuki

发明人： Yoshihiko Ozeki ,  Norihito Tokura ,  Yukio Tsuzuki

IPC分类号： H01L29/66

CPC分类号： H01L27/0611 ,  H01L29/7395 ,  H01L29/8611

摘要： A semiconductor device includes: a semiconductor substrate; a IGBT region including a first region on a first surface of the substrate and providing a channel-forming region and a second region on a second surface of the substrate and providing a collector; a diode region including a third region on the first surface and providing an anode or a cathode and a fourth region on the second surface and providing the anode or the cathode; a periphery region including a fifth region on the first surface and a sixth region on the second surface. The first, third and fifth regions are commonly and electrically coupled, and the second, fourth and sixth regions are commonly and electrically coupled with one another.

摘要翻译： 半导体器件包括：半导体衬底; IGBT区域，包括在所述基板的第一表面上的第一区域，并且在所述基板的第二表面上提供沟道形成区域和第二区域，并提供集电体; 二极管区域，包括在第一表面上的第三区域，并在第二表面上提供阳极或阴极和第四区域，并提供阳极或阴极; 外围区域，包括在第一表面上的第五区域和第二表面上的第六区域。 第一，第三和第五区域通常和电耦合，并且第二，第四和第六区域彼此通常电耦合。

公开(公告)号：US07728382B2

公开(公告)日：2010-06-01

申请号：US12222557

申请日：2008-08-12

申请人： Yukio Tsuzuki ,  Kenji Kouno

发明人： Yukio Tsuzuki ,  Kenji Kouno

IPC分类号： H01L29/76

CPC分类号： H01L27/0676 ,  H01L29/0623 ,  H01L29/7395 ,  H01L29/872

摘要： A semiconductor device includes: a semiconductor substrate including a first conductive type layer; a plurality of IGBT regions, each of which provides an IGBT element; and a plurality of diode regions, each of which provides a diode element. The plurality of IGBT regions and the plurality of diode regions are alternately arranged in the substrate. Each diode region includes a Schottky contact region having a second conductive type. The Schottky contact region is configured to retrieve a minority carrier from the first conductive type layer. The Schottky contact region is disposed in a first surface portion of the first conductive type layer, and adjacent to the IGBT region.

摘要翻译： 半导体器件包括：包括第一导电类型层的半导体衬底; 多个IGBT区域，每个IGBT区域提供IGBT元件; 以及多个二极管区域，每个二极管区域提供二极管元件。 多个IGBT区域和多个二极管区域交替地布置在基板中。 每个二极管区域包括具有第二导电类型的肖特基接触区域。 肖特基接触区域被配置为从第一导电类型层检索少数载流子。 肖特基接触区域设置在第一导电类型层的第一表面部分中，并且与IGBT区域相邻。

公开(公告)号：US20090283798A1

公开(公告)日：2009-11-19

申请号：US12213469

申请日：2008-06-19

申请人： Yukio Tsuzuki ,  Makoto Asai

发明人： Yukio Tsuzuki ,  Makoto Asai

IPC分类号： H01L29/739 ,  H01L27/06 ,  H01L21/8232 ,  H01L21/331

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7806

摘要： A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained.

摘要翻译： 半导体器件包括具有主侧和后侧的n导电型半导体衬底，布置在衬底的主侧上的p导电型层，布置在p导电型中的主侧n导电型区域 层，布置在基板的后侧上的后侧n导电型层，到达基板并穿透主侧n导电型区域和p导电型层的第一沟槽，到达基板的第二沟槽 在p导电型层的内部，嵌入在第二沟槽中并连接到p导电型层的第二电极层。 因此，可以获得其中二极管电池的恢复特性可以在不损害MOS晶体管单元或IGBT单元的性能而不损坏浪涌耐受性的情况下得到的半导体器件。

公开(公告)号：US20090242931A1

公开(公告)日：2009-10-01

申请号：US12385164

申请日：2009-03-31

申请人： Yukio Tsuzuki ,  Kenji Kouno

发明人： Yukio Tsuzuki ,  Kenji Kouno

IPC分类号： H01L27/06 ,  H01L29/739

CPC分类号： H01L29/861 ,  H01L29/0619 ,  H01L29/167 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/8611

摘要： A semiconductor device includes: a substrate; an active element cell area including IGBT cell region and a diode cell region; a first semiconductor region on a first side of the substrate in the active element cell area; a second semiconductor region on a second side of the substrate in the IGBT cell region; a third semiconductor region on the second side in the diode cell region; a fourth semiconductor region on the first side surrounding the active element cell area; a fifth semiconductor region on the first side surrounding the fourth semiconductor region; and a sixth semiconductor region on the second side below the fourth semiconductor region. The second semiconductor region, the third semiconductor region and the sixth semiconductor region are electrically coupled with each other.

摘要翻译： 半导体器件包括：衬底; 包括IGBT单元区域和二极管单元区域的有源元件单元区域; 在所述有源元件单元区域中的所述基板的第一侧上的第一半导体区域; 在所述IGBT单元区域中的所述基板的第二侧上的第二半导体区域; 在二极管单元区域中的第二侧上的第三半导体区域; 围绕所述有源元件单元区域的所述第一侧上的第四半导体区域; 围绕第四半导体区域的第一侧的第五半导体区域; 以及在第四半导体区域下方的第二侧上的第六半导体区域。 第二半导体区域，第三半导体区域和第六半导体区域彼此电耦合。

公开(公告)号：US20070170549A1

公开(公告)日：2007-07-26

申请号：US11649367

申请日：2007-01-04

申请人： Yukio Tsuzuki ,  Norihito Tokura

发明人： Yukio Tsuzuki ,  Norihito Tokura

IPC分类号： H01L27/082

CPC分类号： H01L27/0664 ,  H01L29/0834 ,  H01L29/7397 ,  H01L29/861

摘要： A semiconductor device includes: a substrate having a first side and a second side; an IGBT; and a diode. The substrate includes a first layer, a second layer on the first layer, a first side N region on the second layer, second side N and P regions on the second side of the first layer, a first electrode in a first trench for a gate electrode, a second electrode on the first side N region and in a second trench for an emitter electrode and an anode electrode, and a third electrode on the second side N and P regions for a collector electrode and a cathode. The first trench penetrates the first side N region and the second layer, and reaches the first layer. The second trench penetrates the first side N region, and reaches the second layer.

摘要翻译： 一种半导体器件包括：具有第一面和第二面的衬底; IGBT; 和二极管。 衬底包括第一层，第一层上的第二层，第二层上的第一侧N区，第一层的第二侧上的第二侧N和P区，用于栅极的第一沟槽中的第一电极 电极，第一侧N区域上的第二电极和用于发射电极和阳极电极的第二沟槽中，以及在第二侧的第三电极N和用于集电极和阴极的P区域。 第一沟槽穿过第一侧N区和第二层，并到达第一层。 第二沟槽穿过第一侧N区域并到达第二层。

公开(公告)号：US08847276B2

公开(公告)日：2014-09-30

申请号：US13805740

申请日：2011-06-29

申请人： Hiromitsu Tanabe ,  Kenji Kouno ,  Yukio Tsuzuki

发明人： Hiromitsu Tanabe ,  Kenji Kouno ,  Yukio Tsuzuki

IPC分类号： H01L29/739 ,  H01L27/07 ,  H01L29/66 ,  H01L29/861 ,  H01L29/06

CPC分类号： H01L27/0664 ,  H01L27/0722 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/861

摘要： In a semiconductor device including an IGBT and a freewheeling diode (FWD), W1, W2, and W3 satisfy predetermined formulas. W1 denotes a distance from a boundary between a cathode region and a collector region to a position, where a peripheral-region-side end of the well layer is projected, on a back side of the drift layer. W2 denotes a distance from a boundary between the IGBT and the FWD in a base region to the peripheral-region-side end of the well layer. W3 denotes a distance from the boundary between the cathode region and the collector region to a position, where a boundary between the base region and the well layer is projected, on the back side.

摘要翻译： 在包括IGBT和续流二极管（FWD）的半导体器件中，W1，W2和W3满足预定的公式。 W1表示从阴极区域和集电极区域之间的边界到阱层的周边区域侧端部投射在位于漂移层的背面的位置的距离。 W2表示从基极区域到阱区域的周边区域侧的IGBT与FWD之间的边界的距离。 W3表示从阴极区域和集电极区域之间的边界到背面侧的基底区域和阱层之间的边界的位置的距离。

公开(公告)号：US20120146091A1

公开(公告)日：2012-06-14

申请号：US13313050

申请日：2011-12-07

申请人： Hiromitsu Tanabe ,  Yukio Tsuzuki ,  Kenji Kouno ,  Tomofusa Shiga

发明人： Hiromitsu Tanabe ,  Yukio Tsuzuki ,  Kenji Kouno ,  Tomofusa Shiga

IPC分类号： H01L29/739

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66348

摘要： An insulated gate semiconductor device includes a first conductivity-type semiconductor substrate, a second conductivity-type base layer on a first surface side of the substrate, a trench dividing the base layer into channel and floating layers, and a first conductivity-type emitter region that is formed in the channel layer and in contact with the trench. The semiconductor device includes a gate insulation layer in the trench, a gate electrode on the insulation layer, an emitter electrode electrically connected to the emitter region and the floating layer, a second conductivity-type collector layer in the substrate, and a collector electrode on the collector layer. The floating layer has a lower impurity concentration than the channel layer. The floating layer has a first conductivity-type hole stopper layer located at a predetermined depth from the first surface of the substrate and at least partially spaced from the insulation layer.

摘要翻译： 绝缘栅半导体器件包括第一导电型半导体衬底，在衬底的第一表面侧上的第二导电型基极层，将基极层分为沟道和浮动层的沟槽，以及第一导电型发射极区域 其形成在沟道层中并与沟槽接触。 半导体器件包括沟槽中的栅极绝缘层，绝缘层上的栅极电极，电连接到发射极区域和浮置层的发射极电极，衬底中的第二导电型集电极层，以及集电极电极 集电极层。 浮置层的杂质浓度低于沟道层。 浮动层具有位于距离基板的第一表面预定深度并且至少部分地与绝缘层间隔开的第一导电型孔阻挡层。