公开(公告)号：US5371385A

公开(公告)日：1994-12-06

申请号：US214025

申请日：1994-03-15

申请人： Yutaka Hayashi ,  Masaaki Sato ,  Yoshiki Maeyashiki

发明人： Yutaka Hayashi ,  Masaaki Sato ,  Yoshiki Maeyashiki

IPC分类号： H01L29/74 ,  H01L29/747 ,  H01L29/861 ,  H01L29/87 ,  H01L29/48 ,  H01L29/90

CPC分类号： H01L29/87

摘要： A vertical type surge protection device for absorbing surges of either polarity has a second region forming a first pn junction with a first region, a third region forming a first minority carrier injection junction with respect to the second region, a fourth region forming a second pn junction with the first region and a fifth region forming a second minority carrier injection junction with the fourth region. When the absolute value of a surge voltage applied across the device exceeds the breakdown voltage, either the one of the first and second pn junctions that is reverse biased owing to the surge polarity breaks down or punch-through occurs between the first and third regions or between the first and fifth regions, whereafter breakover ensues as a result of positive feedback. For preventing breakover from being caused by noise having a dV/dt value not greater than a prescribed value, the short-side direction length of the third and fifth regions, in the case they are rectangular, or the diameter thereof, in the case they are circular, is determined on the basis of the prescribed dV/dt value.

摘要翻译： 用于吸收任一极性的浪涌的垂直型浪涌保护装置具有形成与第一区域的第一pn结的第二区域，相对于第二区域形成第一少数载流子注入结的第三区域，形成第二pn的第四区域 与第一区域连接，第五区域与第四区域形成第二少数载流子注入结。 当施加在器件上的浪涌电压的绝对值超过击穿电压时，由于浪涌极性而被反向偏置的第一和第二pn结中的一个发生故障，或者在第一和第三区域之间发生穿通，或者 在第一和第五个地区之间，之后由于积极的反馈而导致突击。 为了防止由具有不大于规定值的dV / dt值的噪声引起的跳动，在第三和第五区域的短边方向长度（在它们为矩形的情况下）或其直径的情况下，在它们 是根据规定的dV / dt值确定的。

公开(公告)号：US5486709A

公开(公告)日：1996-01-23

申请号：US38623

申请日：1993-03-26

申请人： Yutaka Hayashi ,  Masaaki Sato ,  Yoshiki Maeyashiki

发明人： Yutaka Hayashi ,  Masaaki Sato ,  Yoshiki Maeyashiki

IPC分类号： H01L29/74 ,  H01L27/02 ,  H01L29/747 ,  H01L29/861 ,  H01L29/87

CPC分类号： H01L27/0248 ,  H01L29/87

摘要： In a breakover type surge protection device utilizing punch-through that comprises a second semiconductor region forming a first pn junction with a first semiconductor region, a third semiconductor region forming a second pn junction with the second semiconductor region and a fourth semiconductor region forming a third pn junction with the first semiconductor region at a place apart from the second semiconductor region, the second semiconductor region is constituted of a punch-through suppression region portion disposed to cover the corners of the third semiconductor region and a punch-through generation region portion disposed at a place where its thickness can be made uniform. Fabricating surge protection devices according to this configuration reduces variation among their breakover currents and hold currents and increases their surge absorption capacity.

摘要翻译： 在利用穿通的断路式浪涌保护装置中，包括形成与第一半导体区域的第一pn结的第二半导体区域，与第二半导体区域形成第二pn结的第三半导体区域和形成第三半导体区域的第三半导体区域 在与第二半导体区域隔开的位置处与第一半导体区域的pn结，第二半导体区域由设置成覆盖第三半导体区域的角部的穿通抑制区域部分和设置在穿孔产生区域部分 在其厚度可以均匀的地方。 根据这种配置制造浪涌保护装置可以减少其断流和保持电流之间的变化，并增加其浪涌吸收能力。

公开(公告)号：US5376809A

公开(公告)日：1994-12-27

申请号：US192305

申请日：1994-02-04

申请人： Yutaka Hayashi ,  Masaaki Sato ,  Yoshiki Maeyashiki

发明人： Yutaka Hayashi ,  Masaaki Sato ,  Yoshiki Maeyashiki

IPC分类号： H01L29/74 ,  H01L29/744 ,  H01L29/747 ,  H01L29/861 ,  H01L29/87 ,  H01L29/48 ,  H01L29/90

CPC分类号： H01L29/87

摘要： A surge protection device for absorbing surges of either polarity has a second region forming a first pn junction with a first region, a third region capable of injecting first minority carriers into the second region, a fourth region forming a second pn junction with the first region and a fifth region capable of injecting second minority carriers into the fourth region. The surfaces of the fourth region and the fifth region and a first Schottky junction with respect to the first region are in mutual electrical connection with a first ohmic electrode, while the surfaces of the second region and the third region and a second Schottky junction with respect to the first region are in mutual electrical connection with a second ohmic electrode. During the initial stage when a surge voltage applied across the first and second electrodes is in a transient rising state, the dV/dt immunity is increased by majority carrier current flowing into the first region through the Schottky junction forward biased owing to the surge polarity and charging the junction capacitance of the reverse biased pn junction.

摘要翻译： 用于吸收任一极性的浪涌的浪涌保护装置具有形成与第一区域的第一pn结的第二区域，能够将第一少数载流子注入第二区域的第三区域，与第一区域形成第二pn结的第四区域 以及能够将第二少数载体注入第四区域的第五区域。 第四区域和第五区域的表面和相对于第一区域的第一肖特基结与第一欧姆电极相互电连接，而第二区域和第三区域的表面和第二肖特基结的相对于 到第一区域与第二欧姆电极相互电连接。 在施加在第一和第二电极两端的浪涌电压处于瞬态上升状态的初始阶段，由于浪涌极性，通过肖特基结正向偏置流入第一区域的多数载流子电流使得dV / dt抗扰度增加， 充电反向偏置pn结的结电容。

公开(公告)号：US5083185A

公开(公告)日：1992-01-21

申请号：US488457

申请日：1990-02-26

申请人： Yutaka Hayashi ,  Masaaki Sato ,  Yuji Muramatsu ,  Hirofumi Yoshihara ,  Teiji Hasegawa

发明人： Yutaka Hayashi ,  Masaaki Sato ,  Yuji Muramatsu ,  Hirofumi Yoshihara ,  Teiji Hasegawa

IPC分类号： H01L27/02 ,  H01L29/87

CPC分类号： H01L29/87 ,  H01L27/0248

摘要： A surge absorption device includes fundamentally a first semiconductor region, a second semiconductor region forming a pn junction between itself and the first region, a third region determining the effective thickness of the second region, and a fourth region provided in contact with the first region and forming an injection junction for causing first minority carriers of a kind the same as that of minority carriers in the first region to be injected into the first region. When a depletion layer formed by application of reverse bias across the pn junction reaches the third region, a punch-through region is formed in the second region. In this state, when minority carriers are injected from the fourth region into the first region, the minority carriers are absorbed by the second region to constitute the device current.

摘要翻译： 浪涌吸收装置基本上包括第一半导体区域，在其自身与第一区域之间形成pn结的第二半导体区域，确定第二区域的有效厚度的第三区域和与第一区域接触设置的第四区域，以及 形成注入结，以使得与第一区域中的少数载流子相同的第一少数载流子注入第一区域。 当通过在pn结上施加反向偏压形成的耗尽层到达第三区域时，在第二区域中形成穿通区域。 在这种状态下，当少数载流子从第四区域注入第一区域时，少数载流子被第二区域吸收以构成器件电流。

公开(公告)号：US20130224557A1

公开(公告)日：2013-08-29

申请号：US13881747

申请日：2011-10-13

申请人： Tomohiro Hayakawa ,  Takayoshi Hosoya ,  Hiroyuki Kawai ,  Hideo Hayashi ,  Yutaka Hayashi ,  Kohsuke Togashi ,  Naotaka Gotoh

发明人： Tomohiro Hayakawa ,  Takayoshi Hosoya ,  Hiroyuki Kawai ,  Hideo Hayashi ,  Yutaka Hayashi ,  Kohsuke Togashi ,  Naotaka Gotoh

IPC分类号： H01M2/16

CPC分类号： H01M2/1653 ,  C08G18/04 ,  C08G18/4009 ,  H01M2/162 ,  H01M2/1666 ,  H01M2/1686 ,  H01M10/052 ,  Y02E60/122 ,  Y02P70/54

摘要： Provided is a separator for non-aqueous batteries, capable of being usefully used in non-aqueous batteries, and a non-aqueous battery equipped with this separator. The separator for non-aqueous batteries includes: a base layer comprising a fiber aggregate, and an electrolyte-swellable resin layer formed on at least one surface of the base layer, the resin layer comprising a urethane resin (C) obtained by reacting a polyol (A) including a vinyl polymer (a1) and a polyether polyol (a2) with a polyisocyanate (B). The vinyl polymer (a1) has as a main chain a vinyl polymer (a1′) having two hydroxyl groups at one of the termini of the main chain, and a polyoxyethylene chain having a number average molecular weight of 200 to 800 as a side chain, the percentage of the polyoxyethylene chain based on the vinyl polymer (a1) being within the range of 70 mass % to 98 mass %.

摘要翻译： 本发明提供一种能够用于非水电池的非水电池用隔膜，以及配备有该隔膜的非水电池。 非水电池用隔膜包括：包含纤维聚集体的基层和形成在基层的至少一个表面上的电解质溶胀性树脂层，所述树脂层包含聚氨酯树脂（C），其通过使多元醇 （A）包括乙烯基聚合物（a1）和聚醚多元醇（a2）与多异氰酸酯（B）。 乙烯基聚合物（a1）作为主链具有在主链的一个末端具有两个羟基的乙烯基聚合物（a1'）和作为侧链的数均分子量为200〜800的聚氧乙烯链 基于乙烯基聚合物（a1）的聚氧乙烯链的百分比在70质量％至98质量％的范围内。

公开(公告)号：US08450799B2

公开(公告)日：2013-05-28

申请号：US11975923

申请日：2007-10-22

申请人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Hiroaki Takasu ,  Jun Osanai

发明人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Hiroaki Takasu ,  Jun Osanai

IPC分类号： H01L29/34

CPC分类号： H01L29/78615 ,  H01L29/66772

摘要： A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation.

公开(公告)号：US08094484B2

公开(公告)日：2012-01-10

申请号：US12644851

申请日：2009-12-22

申请人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

发明人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

IPC分类号： G11C11/00

CPC分类号： H01L27/24 ,  G11C13/00 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2213/79

摘要： Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the first bit line to connect it to the sense amplifier, specifying the word line and supplying a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the word line voltage becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.

摘要翻译： 公开了一种存储单元阵列，包括分别连接到存储单元的单词和第一位线和第二位线，其中每个存储单元包括MOS晶体管和具有第一和第二导电层的开关元件以及通过施加电阻值而改变电阻值的间隙 通过指定第一位线将其连接到地，写入数据，指定字线并向第二位线提供写入电压，并通过指定第一位线将其连接到感测来读取 放大器，指定字线并将低于写入电压的读取电压提供给第二位线，并且当字线电压变为栅极阈值电压或更高时指定字线，并且驱动电压和 门极阈值电压以下。

公开(公告)号：US20100208522A1

公开(公告)日：2010-08-19

申请号：US12601788

申请日：2008-05-23

申请人： Yutaka Hayashi ,  Kazuhika Matsumoto ,  Takafumi Kamimura

发明人： Yutaka Hayashi ,  Kazuhika Matsumoto ,  Takafumi Kamimura

IPC分类号： G11C16/02 ,  H01L27/105

CPC分类号： H01L29/7881 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28291 ,  H01L29/0657 ,  H01L29/1606 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/6684 ,  H01L29/7781 ,  H01L29/792

摘要： A memory device (1) includes at least a first semiconductor region (100) having a length, a first surface, and a cross section surrounded by the first surface, a memory means (300) provided on the first surface, and a gate (400) provided on the memory means (300), and an equivalent sectional radius of the cross section of the first semiconductor region (100) is set to be equal to or smaller than an equivalent silicon oxide film thickness of the memory means (300) to realize low program voltage. The equivalent sectional radius r of the cross section is set to be 10 nm or less and the gate length is set to be 20 nm or less so that multi-level interval converted to gate voltage becomes a specific value which can be identified under the room temperature.

摘要翻译： 存储器件（1）至少包括具有由第一表面包围的长度，第一表面和横截面的第一半导体区域（100），设置在第一表面上的存储器件（300）和栅极 400），并且将第一半导体区域（100）的横截面的等效截面半径设定为等于或小于存储装置（300）的等效氧化硅膜厚度， 实现低编程电压。 横截面的等效截面半径r设定为10nm以下，栅极长度设定为20nm以下，使得转换为栅极电压的多级间隔成为能够在室内识别的特定值 温度。

公开(公告)号：US20100165696A1

公开(公告)日：2010-07-01

申请号：US12644608

申请日：2009-12-22

申请人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

发明人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

IPC分类号： G11C5/06 ,  G11C7/00

CPC分类号： H01L27/24 ,  G11C13/00 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2213/79

摘要： Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the word line, and specifying the first bit line to supply a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the voltage of the word line becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.

摘要翻译： 公开了一种存储单元阵列，包括分别连接到存储单元的单词和第一位线和第二位线，其中每个存储单元包括MOS晶体管和具有第一和第二导电层的开关元件以及通过施加电阻值而改变电阻值的间隙 通过指定第一位线将其连接到地，写入数据，指定字线并向第二位线提供写入电压，并通过指定字线进行读取，并指定第一位线 以向第二位线提供低于写入电压的读取电压，并且当字线的电压变为栅极阈值电压以上并且驱动电压和栅极阈值电压之和时，指定字线 或更少。

公开(公告)号：US07545018B2

公开(公告)日：2009-06-09

申请号：US11063388

申请日：2005-02-22

申请人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

发明人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

IPC分类号： H01L29/00

CPC分类号： H01L27/0629 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/78645 ,  H01L29/78654

摘要： A high voltage operating field effect transistor has a substrate, a source region and a drain region which are spaced apart from each other in a surface of the substrate, a semiconductor channel formation region disposed in the surface of the substrate between the source region and the drain region, a gate region disposed above the channel formation region, and a gate insulating film region disposed between the channel formation region and the gate region. At least one of a signal electric potential and a signal current is supplied to the source region, and a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential is supplied to the gate region. One end of a rectifying device is connected to the gate region, and a second constant electric potential is supplied to the other end of the rectifying device.

摘要翻译： 高电压工作场效应晶体管具有在基板的表面上彼此间隔开的基板，源极区域和漏极区域，设置在基板的表面中的源极区域与源极区域之间的半导体沟道形成区域， 漏极区域，设置在沟道形成区域上方的栅极区域和设置在沟道形成区域和栅极区域之间的栅极绝缘膜区域。 将信号电位和信号电流中的至少一个提供给源极区域，并且具有绝对值等于或大于根据漏极电流的增减的第一恒定电位变化的偏置电位 电位被提供给栅极区域。 整流装置的一端与栅极区域连接，第二恒定电位被提供给整流装置的另一端。