公开(公告)号：US08140938B2

公开(公告)日：2012-03-20

申请号：US12081940

申请日：2008-04-23

申请人： Yutaka Ito ,  Shigeo Takeuchi

发明人： Yutaka Ito ,  Shigeo Takeuchi

IPC分类号： G11C29/00

CPC分类号： G06F11/1044

摘要： A semiconductor memory device having an error correcting function, includes a memory array having a data area and a check code area, an operation circuit including an encode circuit coupled to the data area and the check code area, and a decode circuit coupled to the check code area, and a control circuit including a first register coupled to the operation circuit.

摘要翻译： 具有误差校正功能的半导体存储器件包括具有数据区和校验码区的存储器阵列，包括耦合到数据区和校验码区的编码电路的操作电路和耦合到检查的解码电路 代码区，以及包括耦合到所述操作电路的第一寄存器的控制电路。

公开(公告)号：US07373584B2

公开(公告)日：2008-05-13

申请号：US11152386

申请日：2005-06-15

申请人： Yutaka Ito ,  Shigeo Takeuchi

发明人： Yutaka Ito ,  Shigeo Takeuchi

IPC分类号： G01C29/00

CPC分类号： G06F11/1044

摘要： A semiconductor memory device includes a memory array having a data area and a check code area and a refresh control for controlling a refresh operation in a data holding state. The device also includes an operation system for executing an encoding operation for generating the check code using a bit string in the data area and a decoding operation for performing the error detection/correction of the data using the check code. Additionally, the device includes an encode controller for controlling an encode process in which, in a change to the data holding state, a first and second code are written in the check code area. Furthermore, the device includes a decode controller for controlling a decode process in which, at the end of the data holding state, first and second bit error correction based on each code are alternately performed, and the first and the second bit error correction are performed at least twice respectively.

摘要翻译： 半导体存储器件包括具有数据区和检查码区的存储器阵列和用于控制数据保持状态下的刷新操作的刷新控制。 该装置还包括一个操作系统，用于执行用于使用数据区域中的比特串产生校验码的编码操作和用于使用校验码执行数据的错误检测/校正的解码操作。 另外，该装置包括编码控制器，用于控制编码处理，其中在数据保持状态的改变中，将第一和第二代码写入校验码区域。 此外，该装置包括用于控制解码处理的解码控制器，其中在数据保持状态结束时交替地执行基于每个代码的第一和第二位错误校正，并执行第一和第二位错误校正 至少两次。

公开(公告)号：US20050286331A1

公开(公告)日：2005-12-29

申请号：US11154625

申请日：2005-06-17

申请人： Yutaka Ito ,  Takeshi Hashimoto ,  Eiji Yamasaki ,  Shigeo Takeuchi ,  Masayuki Kaneda

发明人： Yutaka Ito ,  Takeshi Hashimoto ,  Eiji Yamasaki ,  Shigeo Takeuchi ,  Masayuki Kaneda

IPC分类号： G11C7/00 ,  G11C11/406

CPC分类号： G11C11/406 ,  G11C2211/4062 ,  G11C2211/4067

摘要： Disclosed is a semiconductor memory device including an on-chip ECC circuit and having a data retention mode which includes, in the order of state transition, an encoding state EEST by an error correction circuit in which the error correction circuit carries out calculation of parity bits of data of the memory cells, a burst self-refresh state BSST in which the memory cells are self-refreshed in a burst with a period shorter than in ordinary self-refresh, a power-off state PFST in which an internal power supply circuit is partially turned off, a power-on state PNST in which the internal power supply circuit, partially turned off, is turned on, and a decoding state EDST by the error correction circuit in which the error correction circuit corrects errors of the memory cells. In case a command for exiting from the data retention mode in the encoding state, transition may be made to an idle state IST so that re-entry may be made from the decoding state EDST to the BSST.

摘要翻译： 公开了一种包括片上ECC电路并且具有数据保持模式的半导体存储器件，该数据保持模式按状态转换的顺序包括纠错电路的编码状态EEST，其中纠错电路执行奇偶位的计算 的存储器单元的数据，其中存储器单元以比普通自刷新更短的周期的脉冲串自刷新的脉冲串自刷新状态BSST，电源关闭状态PFST，其中内部电源电路 内部电源电路被部分关断的通电状态PNST和通过纠错电路校正存储单元的错误的纠错电路的解码状态EDST被部分关闭。 在编码状态下从数据保持模式退出的命令的情况下，可以转换到空闲状态IST，以便可以从解码状态EDST到BSST进行重新输入。

公开(公告)号：US07184351B2

公开(公告)日：2007-02-27

申请号：US11154625

申请日：2005-06-17

申请人： Yutaka Ito ,  Takeshi Hashimoto ,  Eiji Yamasaki ,  Shigeo Takeuchi ,  Masayuki Kaneda

发明人： Yutaka Ito ,  Takeshi Hashimoto ,  Eiji Yamasaki ,  Shigeo Takeuchi ,  Masayuki Kaneda

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C2211/4062 ,  G11C2211/4067

摘要： A semiconductor memory device including an on-chip ECC circuit and having a data retention mode which includes, in the order of state transition, an encoding state EEST by an error correction circuit in which the error correction circuit carries out calculation of parity bits of data of the memory cells, a burst self-refresh state BSST in which the memory cells are self-refreshed in a burst with a period shorter than in ordinary self-refresh, a power-off state PFST in which an internal power supply circuit is partially turned off, a power-on state PNST in which the internal power supply circuit, partially turned off, is turned on, and a decoding state EDST by the error correction circuit in which the error correction circuit corrects errors of the memory cells. In case a command for exiting from the data retention mode in the encoding state, transition may be made to an idle state IST so that re-entry may be made from the decoding state EDST to the BSST.

摘要翻译： 一种包括片上ECC电路并具有数据保持模式的半导体存储器件，该数据保持模式按照状态转换的顺序包括纠错电路中的纠错电路的编码状态EEST，其中错误校正电路执行数据的奇偶校验位的计算 存储单元的突发自刷新状态BSST，其中存储器单元以比普通自刷新更短的周期的脉冲串进行自刷新，其中内部电源电路部分地处于断电状态PFST 关闭其中部分关闭的内部电源电路接通的上电状态PNST，以及其中纠错电路校正存储器单元的错误的纠错电路的解码状态EDST。 在编码状态下从数据保持模式退出的命令的情况下，可以转换到空闲状态IST，以便可以从解码状态EDST到BSST进行重新输入。

公开(公告)号：US20050283704A1

公开(公告)日：2005-12-22

申请号：US11152386

申请日：2005-06-15

申请人： Yutaka Ito ,  Shigeo Takeuchi

发明人： Yutaka Ito ,  Shigeo Takeuchi

IPC分类号： G06F11/10 ,  H03M13/00

CPC分类号： G06F11/1044

摘要： A semiconductor memory device comprising: a memory array having a data area and a check code area; refresh control means which controls a refresh operation in a data holding state; operation means which executes an encoding operation for generating the check code using a bit string in the data area, and executes a decoding operation for performing the error detection/correction of the data using the check code; encode control means for controlling an encode process in which in a change to the data holding state, a first and second code are written in the check code area; and decode control means for controlling a decode process in which at the end of the data holding state, first and second bit error correction based on each code are alternately performed, and the first and the second bit error correction are performed at least twice respectively.

摘要翻译： 一种半导体存储器件，包括：具有数据区和校验码区的存储器阵列; 刷新控制装置，其控制数据保持状态下的刷新操作; 执行用于使用数据区域中的比特串生成校验码的编码操作的操作装置，并且执行使用校验码执行数据的错误检测/校正的解码操作; 编码控制装置，用于控制编码处理，其中在数据保持状态的改变中，将第一和第二代码写入校验码区域; 以及用于控制解码处理的解码控制装置，其中在数据保持状态结束时交替执行基于每个代码的第一和第二位错误校正，并且分别执行至少两次执行第一和第二位错误校正。

公开(公告)号：US20140308592A1

公开(公告)日：2014-10-16

申请号：US14342636

申请日：2012-09-05

申请人： Hajime Maki ,  Yutaka Ito ,  Yoshinari Sawabe ,  Kenichiro Ota

发明人： Hajime Maki ,  Yutaka Ito ,  Yoshinari Sawabe ,  Kenichiro Ota

IPC分类号： H01M4/92 ,  H01M4/88

CPC分类号： H01M4/926 ,  H01M4/8807 ,  H01M4/8853 ,  H01M4/8878 ,  H01M4/9041 ,  H01M4/925

摘要： A method of manufacturing a dispersion liquid for an electrode catalyst, the method comprising a step of supporting a precious metal on the surface of a carrier by an electrodeposition process using a raw material mixed solution in which a particulate carrier is dispersed in a solvent and a compound including the precious metal element is dissolved in the solvent, wherein the carrier has oxygen reduction capability and is free of precious metal elements.

摘要翻译： 一种制造电极催化剂用分散液的方法，该方法包括以下步骤：通过使用其中将颗粒状载体分散在溶剂中的原料混合溶液的电沉积工艺将贵金属担载在载体表面上， 包含贵金属元素的化合物溶解在溶剂中，其中载体具有氧还原能力并且不含贵金属元素。

公开(公告)号：US20130192985A1

公开(公告)日：2013-08-01

申请号：US13808142

申请日：2011-07-06

申请人： Takeshi Hattori ,  Yutaka Ito ,  Hajime Maki ,  Hideto Imai ,  Kenichiro Ota

发明人： Takeshi Hattori ,  Yutaka Ito ,  Hajime Maki ,  Hideto Imai ,  Kenichiro Ota

IPC分类号： C25B11/04 ,  H01M4/86

CPC分类号： C25B11/0405 ,  C25B11/0415 ,  C25B11/0447 ,  H01M4/8605 ,  H01M4/8652 ,  H01M4/8657 ,  H01M4/8673 ,  H01M4/88 ,  H01M4/9016

摘要： An electrode catalyst, including: a metal compound which contains an oxygen atom and at least one metal element selected from a group consisting of Group 4 elements and Group 5 elements in the long-form periodic table, and a carbonaceous material which covers at least part of the metal compound; wherein an oxygen deficiency index, which is represented as an inverse number of a peak value of a first nearest neighbor element in a radial distribution function obtained by Fourier-transforming an EXAFS oscillation in EXAFS measurement of the metal element, is 0.125 to 0.170; and a crystallinity index, which is represented as a peak value of a second nearest neighbor element in the radial distribution function, is 4.5 to 8.0.

摘要翻译： 一种电极催化剂，包括：含有氧原子的金属化合物和选自长型周期表中的第4族元素和第5族元素的至少一种金属元素，以及覆盖至少部分的碳质材料 的金属化合物; 其中，通过对金属元素的EXAFS测量中的EXAFS振荡进行傅里叶变换而获得的径向分布函数中的第一最近相邻元素的峰值的倒数表示的氧缺乏指数为0.125〜0.170， 在径向分布函数中表示为第二最近相邻元素的峰值的结晶度指数为4.5〜8.0。

公开(公告)号：US08437195B2

公开(公告)日：2013-05-07

申请号：US13355841

申请日：2012-01-23

申请人： Yutaka Ito ,  Adrian J. Drexler ,  Brandi M. Jones

发明人： Yutaka Ito ,  Adrian J. Drexler ,  Brandi M. Jones

IPC分类号： G11C11/34

CPC分类号： G11C11/4074 ,  G11C5/14 ,  G11C5/144 ,  G11C7/20 ,  G11C11/4072

摘要： Some embodiments include apparatus, systems, and methods having a voltage generator to generate a voltage, a memory cell including a storage node associated with a storage node voltage, and a power controller to provide a signal to the voltage generator such that the voltage generated by the voltage generator rises from a voltage less than a reference voltage to a voltage less than the storage node voltage, and such that the voltage generated by the voltage generator is less than or equal to the storage node voltage, at least partially in response to the apparatus entering into a mode. Other embodiments are described.

摘要翻译： 一些实施例包括具有用于产生电压的电压发生器的装置，系统和方法，包括与存储节点电压相关联的存储节点的存储单元和功率控制器，以向电压发生器提供信号，使得由 电压发生器从小于参考电压的电压升高到小于存储节点电压的电压，并且使得由电压发生器产生的电压小于或等于存储节点电压，至少部分地响应于 进入模式的装置。 描述其他实施例。

公开(公告)号：US20130062086A1

公开(公告)日：2013-03-14

申请号：US13698231

申请日：2011-04-12

申请人： Yutaka Ito ,  Katsuhiro Oomori ,  Mizuho Nakamura ,  Tomomasa Nishikawa ,  Hironori Mashiko

发明人： Yutaka Ito ,  Katsuhiro Oomori ,  Mizuho Nakamura ,  Tomomasa Nishikawa ,  Hironori Mashiko

IPC分类号： B25B21/02 ,  B25B23/147

CPC分类号： B25B23/1405 ,  B25B23/1475

摘要： The present invention provides a power tool for tightening a fastener. The power tool includes a motor, a hammer, an anvil, and a control unit. The hammer is intermittently or continuously rotatable in a forward direction by the motor. The anvil is impacted by the hammer rotated in the forward direction. The control unit controls the hammer to continuously rotate at a first number of rotations, and to intermittently rotate at a second number of rotations lower than the first number of rotations when a prescribed time has elapsed from the rotation of the hammer at the first number of rotations, and then to intermittently rotate at a third number of rotations lower than the second number of rotations when a predetermined time has elapsed from the rotation of the hammer at the second number of rotations.

摘要翻译： 本发明提供一种用于紧固紧固件的电动工具。 电动工具包括马达，锤子，砧座和控制单元。 锤子通过马达在向前方向间歇地或连续地旋转。 砧座被向前方向旋转的锤子撞击。 控制单元控制锤以第一转数连续旋转，并且当从第一数量的锤的旋转经过规定的时间以后，以比第一转数低的第二转数间歇地旋转 然后当在第二转数时从锤的旋转经过预定时间时，以低于第二转数的第三转数间歇地旋转。

公开(公告)号：US08386886B2

公开(公告)日：2013-02-26

申请号：US13273765

申请日：2011-10-14

申请人： Yutaka Ito ,  Takuya Nakanishi

发明人： Yutaka Ito ,  Takuya Nakanishi

IPC分类号： G11C29/00

CPC分类号： G06F11/106 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/23 ,  H03M13/2957

摘要： Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving mode, memory cells in the DRAM device may be refreshed using a self-refresh operation. This self-refresh operation may allow bit errors to occur in the DRAM device. However, by employing error correction coding (ECC), embodiments of the present invention may detect and correct these potential errors that may occur in the power-saving mode. Furthermore, a partial ECC check cycle is employed to check and correct a sub-set of the memory cells during a periodic self-refresh process that occurs during the power-saving mode.

摘要翻译： 公开了在省电模式期间保存，验证和校正DRAM装置中的数据的方法，装置和系统。 在省电模式下，可以使用自刷新操作刷新DRAM装置中的存储单元。 该自刷新操作可能允许在DRAM器件中发生位错误。 然而，通过采用纠错编码（ECC），本发明的实施例可以检测和校正在省电模式下可能发生的这些潜在错误。 此外，在省电模式期间发生的周期性自刷新过程中，采用部分ECC校验周期来检查和校正存储器单元的子集。