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    Data transmitter
    1.
    发明授权
    Data transmitter 失效
    数据发送器

    公开(公告)号：US06542552B1

    公开(公告)日：2003-04-01

    申请号：US09468830

    申请日：1999-12-22

    申请人： Takefumi Yoshikawa ,  Yutaka Terada

    发明人： Takefumi Yoshikawa ,  Yutaka Terada

    IPC分类号： H03B300

    CPC分类号： G06F1/10 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0091 ,  H04L7/04

    摘要： A data transmitter according to the present invention includes driver, transmission line and receiver. The receiver includes a transition pulse generator for generating a transition pulse simultaneously with the transition of a data signal output from the driver. If an edge of an internal clock signal overlaps with the transition pulse being applied, then the receiver does not latch the data signal in synchronism with the edge of the internal clock signal. Instead, the receiver obtains and retains a data value opposite to the previous cycle one. On the other hand, while no transition pulses are being applied, the receiver latches the data signal normally responsive to the internal clock signal. Accordingly, the receiver can always accurately retain the very data transmitted through the transmission line, thus improving the reliability of the data received and realizing high-speed data transmission even if the internal clock signal has lagged with respect to the data signal.

    摘要翻译： 根据本发明的数据发送器包括驱动器，传输线和接收器。 接收机包括转换脉冲发生器，用于与从驾驶员输出的数据信号的转变同时产生转换脉冲。 如果内部时钟信号的边沿与施加的转换脉冲重叠，则接收器不会与内部时钟信号的边沿同步地锁存数据信号。 相反，接收器获得并保留与前一个周期相反的数据值。 另一方面，当没有施加转换脉冲时，接收器通常响应于内部时钟信号来锁存数据信号。 因此，即使内部时钟信号相对于数据信号滞后，接收机总是可以准确地保持通过传输线传输的非常数据，从而提高接收的数据的可靠性并实现高速数据传输。

    Input circuit and output circuit
    2.
    发明授权
    Input circuit and output circuit 失效
    输入电路和输出电路

    公开(公告)号：US06829316B1

    公开(公告)日：2004-12-07

    申请号：US09299659

    申请日：1999-04-27

    申请人： Yutaka Terada ,  Takefumi Yoshikawa

    发明人： Yutaka Terada ,  Takefumi Yoshikawa

    IPC分类号： H04L700

    CPC分类号： G11C7/1093 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/22

    摘要： An input circuit includes: a comparator; first and second delay circuits; a selector; an input buffer; and a holding circuit. The comparator compares the leading and/or trailing edges of a data signal, supplied from the input buffer, to an edge of a clock signal on which the data signal is intended to be latched. Based on the results of the comparison, the first and second delay circuits delay the clock signal for respectively predetermined amounts of time. If the data signal is logically high, then the selector selects a delayed clock signal supplied from the first delay circuit. Alternatively, if the data signal is logically low, then the selector selects another delayed clock signal supplied from the second delay circuit. Then, the delayed clock signal, selected by the selector, is latched in the holding circuit. The input circuit with such a configuration prevents skewing from being caused by a difference in length between the transition interval of the data signal from H into L level and that of the data signal from L into H level. As a result, data can be transferred at a much higher speed even if the clock frequency is very high.

    摘要翻译： 输入电路包括：比较器; 第一和第二延迟电路; 选择器 一个输入缓冲区; 和保持电路。 比较器将从输入缓冲器提供的数据信号的前沿和/或后沿比较到要锁存数据信号的时钟信号的边沿。 基于比较结果，第一和第二延迟电路分别延迟时钟信号预定的时间量。 如果数据信号逻辑高，则选择器选择从第一延迟电路提供的延迟时钟信号。 或者，如果数据信号在逻辑上低，则选择器选择从第二延迟电路提供的另一延迟时钟信号。 然后，由选择器选择的延迟时钟信号被锁存在保持电路中。 具有这种配置的输入电路防止由数据信号从H变为L电平的过渡间隔和从L变为H电平的数据信号之间的长度差引起的偏移。 因此，即使时钟频率非常高，也可以以更高的速度传输数据。

    Input circuit and output circuit
    3.
    发明授权
    Input circuit and output circuit 有权
    输入电路和输出电路

    公开(公告)号：US07149267B2

    公开(公告)日：2006-12-12

    申请号：US10995124

    申请日：2004-11-24

    申请人： Yutaka Terada ,  Takefumi Yoshikawa

    发明人： Yutaka Terada ,  Takefumi Yoshikawa

    IPC分类号： H04L7/00

    CPC分类号： G11C7/1093 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/22

    摘要： An input circuit includes: a comparator; first and second delay circuits; a selector; an input buffer; and a holding circuit. The comparator compares the leading and/or trailing edges of a data signal, supplied from the input buffer, to an edge of a clock signal on which the data signal is intended to be latched. Based on the results of the comparison, the first and second delay circuits delay the clock signal for respectively predetermined amounts of time. If the data signal is logically high, then the selector selects a delayed clock signal supplied from the first delay circuit. Alternatively, if the data signal is logically low, then the selector selects another delayed clock signal supplied from the second delay circuit. Then, the delayed clock signal, selected by the selector, is latched in the holding circuit. The input circuit with such a configuration prevents skewing from being caused by a difference in length between the transition interval of the data signal from H into L level and that of the data signal from L into H level. As a result, data can be transferred at a much higher speed even if the clock frequency is very high.

    摘要翻译： 输入电路包括：比较器; 第一和第二延迟电路; 选择器 一个输入缓冲区; 和保持电路。 比较器将从输入缓冲器提供的数据信号的前沿和/或后沿比较到要锁存数据信号的时钟信号的边沿。 基于比较结果，第一和第二延迟电路分别延迟时钟信号预定的时间量。 如果数据信号逻辑高，则选择器选择从第一延迟电路提供的延迟时钟信号。 或者，如果数据信号在逻辑上低，则选择器选择从第二延迟电路提供的另一延迟时钟信号。 然后，由选择器选择的延迟时钟信号被锁存在保持电路中。 具有这种配置的输入电路防止由数据信号从H变为L电平的过渡间隔和从L变为H电平的数据信号之间的长度差引起的偏移。 因此，即使时钟频率非常高，也可以以更高的速度传输数据。

    Input circuit and output circuit
    4.
    发明申请
    Input circuit and output circuit 有权
    输入电路和输出电路

    公开(公告)号：US20050094426A1

    公开(公告)日：2005-05-05

    申请号：US10995124

    申请日：2004-11-24

    申请人： Yutaka Terada ,  Takefumi Yoshikawa

    发明人： Yutaka Terada ,  Takefumi Yoshikawa

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C5/06

    CPC分类号： G11C7/1093 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/22

    摘要： An input circuit includes: a comparator; first and second delay circuits; a selector; an input buffer; and a holding circuit. The comparator compares the leading and/or trailing edges of a data signal, supplied from the input buffer, to an edge of a clock signal on which the data signal is intended to be latched. Based on the results of the comparison, the first and second delay circuits delay the clock signal for respectively predetermined amounts of time. If the data signal is logically high, then the selector selects a delayed clock signal supplied from the first delay circuit. Alternatively, if the data signal is logically low, then the selector selects another delayed clock signal supplied from the second delay circuit. Then, the delayed clock signal, selected by the selector, is latched in the holding circuit. The input circuit with such a configuration prevents skewing from being caused by a difference in length between the transition interval of the data signal from H into L level and that of the data signal from L into H level. As a result, data can be transferred at a much higher speed even if the clock frequency is very high.

    摘要翻译： 输入电路包括：比较器; 第一和第二延迟电路; 选择器 一个输入缓冲区; 和保持电路。 比较器将从输入缓冲器提供的数据信号的前沿和/或后沿比较到要锁存数据信号的时钟信号的边沿。 基于比较结果，第一和第二延迟电路将时钟信号分别延迟预定的时间量。 如果数据信号逻辑高，则选择器选择从第一延迟电路提供的延迟时钟信号。 或者，如果数据信号在逻辑上低，则选择器选择从第二延迟电路提供的另一延迟时钟信号。 然后，由选择器选择的延迟时钟信号被锁存在保持电路中。 具有这种配置的输入电路防止由数据信号从H变为L电平的过渡间隔和从L变为H电平的数据信号之间的长度差引起的偏移。 因此，即使时钟频率非常高，也可以以更高的速度传输数据。

    Automatic wire supply system of wire cut electrodischarge machine
    5.
    发明授权
    Automatic wire supply system of wire cut electrodischarge machine 失效
    线切割放电机自动供线系统

    公开(公告)号：US06698639B1

    公开(公告)日：2004-03-02

    申请号：US10111083

    申请日：2002-04-19

    申请人： Yoichi Otomo ,  Hisashi Yamada ,  Yutaka Terada

    发明人： Yoichi Otomo ,  Hisashi Yamada ,  Yutaka Terada

    IPC分类号： B65H2000

    CPC分类号： B23H7/101 ,  B23H7/102

    摘要： An automatic wire feeder of a wire electric discharge machine in which electric discharge is generated between a traveling wire electrode (1) and a workpiece so as to machine the workpiece by the electric discharge energy, comprises: a feed roller (2) for feeding the wire electrode (1); a slider block (11) supported being capable of going up and down; a guide pipe (9), fixed to the slider block (11), for guiding the wire electrode (1); a hollow member (10), fixed to the slider block (11), the outer diameter of which is reduced in a wire feed direction; and a pressurized gas supply for supplying pressurized gas toward the outer diameter of the hollow member (10), wherein a forward end section of the hollow member (10) is inserted into an inner diameter section of an upper section of the guide pipe (9) while a predetermined overlapping length L is kept, a predetermined clearance D1 is formed between the inner diameter of the guide pipe (9) and the outer diameter of the forward end section of the hollow member (10), and a thrust is given to the wire electrode (1) by pressurized gas, which is supplied by the pressurized gas supply. By the conveyance force of pressurized gas flowing in the guide pipe (9), the wire electrode (1) can be automatically fed with high reliability.

    摘要翻译： 一种电线放电机的自动送丝机，其特征在于，在行走线电极（1）和工件之间产生放电以便通过放电能量加工工件的线放电机，包括：馈送辊（2） 线电极（1）; 支撑能够上下移动的滑动块（11）; 导向管（9），其固定到所述滑动块（11），用于引导所述线电极（1）; 固定在所述滑动块（11）上的中空构件（10），其外径在送丝方向上减小; 以及用于向中空构件（10）的外径供给加压气体的加压气体供给装置，其中，中空构件（10）的前端部插入导管（9）的上部的内径部 ），同时保持预定的重叠长度L，在引导管（9）的内径和中空构件（10）的前端部分的外径之间形成预定的间隙D1， 所述线电极（1）由加压气体供给，由加压气体供给。 通过在导管（9）中流动的加压气体的输送力，线电极（1）能够以高可靠性自动进给。

    Offsetting comparator device and comparator circuit
    6.
    发明授权
    Offsetting comparator device and comparator circuit 失效
    偏移比较器器件和比较器电路

    公开(公告)号：US06339355B1

    公开(公告)日：2002-01-15

    申请号：US09461381

    申请日：1999-12-15

    申请人： Hiroyuki Yamauchi ,  Yutaka Terada

    发明人： Hiroyuki Yamauchi ,  Yutaka Terada

    IPC分类号： H03L500

    CPC分类号： H03F3/45717

    摘要： An offsetting comparator device includes master and slave comparator circuits and a reference differential voltage generator. The master comparator circuit supplies a sensed current corresponding to a potential difference represented by a differential signal on a transmission line. The reference differential voltage generator generates a reference differential voltage based on an intermediate potential of the differential signal. And the slave comparator circuit supplies a current corresponding to the potential difference as offset current. The offsetting comparator device outputs a differential current between the sensed and offset currents and therefore shows an offset in its input/output characteristics. The master and slave comparator circuits have the same circuit configuration. Thus, if the characteristic of the sensed current output from the master comparator circuit has changed due to a potential level variation of the differential signal, then the characteristic of the offset current also changes similarly. Thus, the offsetting comparator device can obtain a constant offset voltage even if the potential level of the differential signal has changed.

    摘要翻译： 偏置比较器装置包括主比较器电路和参考差分电压发生器。 主比较器电路在传输线上提供与由差分信号表示的电位差相对应的感测电流。 参考差分电压发生器基于差分信号的中间电位产生参考差分电压。 并且从比较器电路提供对应于电位差的电流作为偏移电流。 偏移比较器装置在感测和偏移电流之间输出差分电流，因此在其输入/输出特性中显示偏移。 主从比较器电路具有相同的电路配置。 因此，如果从主比较器电路输出的检测电流的特性由于差分信号的电位电平变化而改变，则偏移电流的特性也发生类似变化。 因此，即使差分信号的电位电平已经改变，偏移比较器装置也可获得恒定的偏移电压。

    Semiconductor integrated circuit and semiconductor integrated circuit system having serially interconnectable data buses
    7.
    发明授权
    Semiconductor integrated circuit and semiconductor integrated circuit system having serially interconnectable data buses 有权
    具有串行可互连数据总线的半导体集成电路和半导体集成电路系统

    公开(公告)号：US06297675B1

    公开(公告)日：2001-10-02

    申请号：US09478530

    申请日：2000-01-06

    申请人： Hironori Akamatsu ,  Yutaka Terada ,  Takashi Hirata ,  Yukio Arima ,  Satoshi Takahashi ,  Tadahiro Yoshida ,  Yoshihide Komatsu ,  Hiroyuki Yamauchi

    发明人： Hironori Akamatsu ,  Yutaka Terada ,  Takashi Hirata ,  Yukio Arima ,  Satoshi Takahashi ,  Tadahiro Yoshida ,  Yoshihide Komatsu ,  Hiroyuki Yamauchi

    IPC分类号： H03B100

    CPC分类号： H03K19/018514 ,  Y10T307/549

    摘要： A data line pair and a strobe line pair are provided between first and second chips to exchange data therebetween. The first chip includes an output circuit and a controller for controlling the output circuit. The second chip includes an input circuit. For example, the output circuit supplies a direct current from a power supply to one of the data lines. Then, the input circuit feeds back the received current to the output circuit through a pair of terminal resistors and the other data line. Subsequently, the output circuit supplies the fed back direct current to one of the strobe lines. In response, the input circuit feeds back the received current again to the output circuit through another pair of terminal resistors and the other strobe line. And then the fed back current is drained to the ground. Thus, compared to driving the data and strobe line pairs separately with the same amount of current supplied, the current dissipation can be halved. In this manner, the present invention is applicable to reduction of current dissipation when data should be transmitted at high speeds through multiple data bus pairs that are driven with a current supplied.

    摘要翻译： 在第一和第二芯片之间提供数据线对和选通线对，以在它们之间交换数据。 第一芯片包括输出电路和用于控制输出电路的控制器。 第二芯片包括输入电路。 例如，输出电路将电流从电源提供给数据线之一。 然后，输入电路通过一对端子电阻和另一条数据线将接收的电流反馈到输出电路。 随后，输出电路将反馈的直流电流提供给选通线之一。 作为响应，输入电路通过另一对端子电阻器和另一个选通线路将接收到的电流再次反馈到输出电路。 然后将反馈电流排到地面。 因此，与以相同的电流量驱动数据和选通线对相比，电流消耗可以减半。 以这种方式，本发明可应用于当通过以所提供的电流驱动的多个数据总线对以高速传输数据时，减少电流消耗。

    Time counting circuit and counter circuit
    8.
    发明授权
    Time counting circuit and counter circuit 失效
    计时电路和计数器电路

    公开(公告)号：US5828717A

    公开(公告)日：1998-10-27

    申请号：US624960

    申请日：1996-03-27

    申请人： Keiichi Kusumoto ,  Shiro Dosho ,  Yutaka Terada ,  Akira Matsuzawa

    发明人： Keiichi Kusumoto ,  Shiro Dosho ,  Yutaka Terada ,  Akira Matsuzawa

    IPC分类号： G01R29/027 ,  G01C21/00

    CPC分类号： G01R29/0273

    摘要： There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption. An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition. A time-difference operating circuit corrects the numeric data outputted from the signal converting circuit based on the number of circulations of signal transition outputted from the counter circuit to provide time data, while calculating and outputting the pulse spacing of the pulse signal to be measured.

    摘要翻译： 提供了一种用于以高精度和低功耗测量脉冲信号的脉冲间隔的时间计数电路。 由连接在环上的奇数个反相器组成的逆变器环振荡，并且一个信号转换发生在似乎在逆变器环周围似乎循环。 连接到构成逆变器环的逆变器的各个输出端子的保持电路在待测脉冲信号的上升沿同时输出从逆变器输出的信号。 然后，输出的信号由信号转换电路转换成数字数据。 连接到构成逆变器环的逆变器之一的输出端的计数器电路对信号转换的循环数进行计数。 时差操作电路根据从计数器电路输出的信号转换的循环数来校正从信号转换电路输出的数字数据，以提供时间数据，同时计算并输出要测量的脉冲信号的脉冲间隔。