公开(公告)号：US20120112315A1

公开(公告)日：2012-05-10

申请号：US12950973

申请日：2010-11-19

申请人： ZHEN CHEN ,  Yung Feng Lin ,  Lin Huang

发明人： ZHEN CHEN ,  Yung Feng Lin ,  Lin Huang

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention provide a method and system for manufacturing copper-based capacitor on an integrated circuit. For example, the integrated circuit is associated with a channel length of less than 0.13 um. It is to be appreciated that, depending upon application, the present invention provides a more improved method for manufacturing capacitors and thus allow MIM capacitors to be manufactured at smaller dimensions. The method includes a step for providing a substrate. The method also includes a step for providing a layer of inter-metal dielectric overlaying the substrate. The method additionally includes a step for providing a bottom layer. The bottom layer includes a first portion and a second portion. The first portion can be characterized as electrically conductive. In addition, the method includes a step for providing a first insulating layer overlaying the bottom layer.

摘要翻译： 本发明的实施例提供了一种用于在集成电路上制造铜基电容器的方法和系统。 例如，集成电路与小于0.13um的通道长度相关联。 应当理解，根据应用，本发明提供了一种用于制造电容器的更加改进的方法，从而允许以更小的尺寸制造MIM电容器。 该方法包括提供衬底的步骤。 该方法还包括提供覆盖衬底的金属间电介质层的步骤。 该方法另外包括用于提供底层的步骤。 底层包括第一部分和第二部分。 第一部分可以被表征为导电的。 此外，该方法包括提供覆盖底层的第一绝缘层的步骤。

公开(公告)号：US08395200B2

公开(公告)日：2013-03-12

申请号：US12950973

申请日：2010-11-19

申请人： Zhen Chen ,  Yung Feng Lin ,  Lin Huang

发明人： Zhen Chen ,  Yung Feng Lin ,  Lin Huang

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L21/20

CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a capacitor on an integrated circuit includes providing an inter-metal dielectric layer on a substrate, a bottom layer having a first and second portions, a first insulating layer having via plug openings on the bottom layer, and via plugs disposed in the via plug openings. The via plugs include a first and second via plugs and are electrically coupled to the first portion of the bottom layer. The method further includes providing a capacitor layer having a first barrier metal layer coupled to the first via plug. The capacitor layer also has a capacitor dielectric layer overlying the first barrier metal layer and a second barrier metal overlying the capacitor dielectric layer. The method further includes defining a first and second capacitor layer portions. The first capacitor layer portion has two opposite sides and spacers disposed on their surface.

摘要翻译： 一种在集成电路上制造电容器的方法包括在基片上提供金属间电介质层，底层具有第一和第二部分，在底层上具有通孔插头开口的第一绝缘层，以及设置在 通孔插头开口。 通孔塞包括第一和第二通孔塞，并且电耦合到底层的第一部分。 该方法还包括提供具有耦合到第一通孔插头的第一阻挡金属层的电容器层。 电容器层还具有覆盖第一阻挡金属层的电容器电介质层和覆盖电容器介电层的第二阻挡金属。 该方法还包括限定第一和第二电容器层部分。 第一电容器层部分具有设置在其表面上的两个相对侧和间隔物。

公开(公告)号：US08324692B2

公开(公告)日：2012-12-04

申请号：US12953426

申请日：2010-11-23

申请人： Zhen Chen ,  Yung Feng Lin ,  Lin Huang

发明人： Zhen Chen ,  Yung Feng Lin ,  Lin Huang

IPC分类号： H01L27/11

CPC分类号： H01L27/13 ,  H01F17/0006 ,  H01F2017/0046 ,  H01F2017/0073 ,  H01F2017/0086 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating an integrated inductor device includes providing a silicon substrate and forming a thickness of an insulating layer overlying the silicon substrate. The insulating layer includes a dummy structure within a portion of the thickness. The method includes forming an inductor having a first portion and a second portion. The first portion includes a spiral coil of conductor lines. The method also includes exposing the dummy structure by forming an opening in the insulating layer and removing the dummy structure to form a cavity underlying the inductor to reduce a dielectric constant and to increase a Q value of the inductor. The method includes using aluminum or copper for the dummy structures. The method includes dry etching the insulator and wet etching the dummy structure. The method also includes forming the inductors using aluminum or copper.

摘要翻译： 制造集成电感器件的方法包括提供硅衬底并形成覆盖硅衬底的绝缘层的厚度。 绝缘层在厚度的一部分内包括虚拟结构。 该方法包括形成具有第一部分和第二部分的电感器。 第一部分包括导线的螺旋线圈。 该方法还包括通过在绝缘层中形成开口并去除虚拟结构以形成电感器下面的空腔来暴露虚拟结构，以降低介电常数并增加电感器的Q值。 该方法包括使用铝或铜作为虚拟结构。 该方法包括干法蚀刻绝缘体并湿式蚀刻虚拟结构。 该方法还包括使用铝或铜形成电感器。

公开(公告)号：US20110304013A1

公开(公告)日：2011-12-15

申请号：US12953426

申请日：2010-11-23

申请人： ZHEN CHEN ,  Yung Feng Lin ,  Lin Huang

发明人： ZHEN CHEN ,  Yung Feng Lin ,  Lin Huang

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L27/13 ,  H01F17/0006 ,  H01F2017/0046 ,  H01F2017/0073 ,  H01F2017/0086 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating an integrated inductor device includes providing a silicon substrate and forming a thickness of an insulating layer overlying the silicon substrate. The insulating layer includes a dummy structure within a portion of the thickness. The method includes forming an inductor having a first portion and a second portion. The first portion includes a spiral coil of conductor lines. The method also includes exposing the dummy structure by forming an opening in the insulating layer and removing the dummy structure to form a cavity underlying the inductor to reduce a dielectric constant and to increase a Q value of the inductor. The method includes using aluminum or copper for the dummy structures. The method includes dry etching the insulator and wet etching the dummy structure. The method also includes forming the inductors using aluminum or copper.

摘要翻译： 制造集成电感器件的方法包括提供硅衬底并形成覆盖硅衬底的绝缘层的厚度。 绝缘层在厚度的一部分内包括虚拟结构。 该方法包括形成具有第一部分和第二部分的电感器。 第一部分包括导线的螺旋线圈。 该方法还包括通过在绝缘层中形成开口并去除虚拟结构以形成电感器下面的空腔来暴露虚拟结构，以降低介电常数并增加电感器的Q值。 该方法包括使用铝或铜作为虚拟结构。 该方法包括干法蚀刻绝缘体并湿式蚀刻虚拟结构。 该方法还包括使用铝或铜形成电感器。

公开(公告)号：US20120139020A1

公开(公告)日：2012-06-07

申请号：US12986123

申请日：2011-01-06

申请人： Zhen Chen ,  Yung Feng Lin

发明人： Zhen Chen ,  Yung Feng Lin

IPC分类号： H01L27/06 ,  H01L21/336

CPC分类号： H01L29/93 ,  H01L29/66181 ,  H01L29/94

摘要： A method for forming a variable capacitor includes providing a semiconductor substrate of a first conductivity type and forming an active region of a second conductivity type within the substrate. The method forms a first dielectric layer overlying the active region. The method provides a conductive gate layer over the first dielectric layer and selectively patterns the conductive gate layer to form a plurality of holes in the conductive gate layer. A perimeter of the holes and a spacing between a first and a second holes are selective to provide a high quality factor (Q) of the capacitor. The method implants impurities of the second conductivity type into the active region through the plurality of holes in the conductive layer. The method also includes providing a second dielectric layer and patterning the second dielectric layer to form contacts to the active region and the gate.

摘要翻译： 形成可变电容器的方法包括提供第一导电类型的半导体衬底，并在衬底内形成第二导电类型的有源区。 该方法形成覆盖有源区的第一介电层。 该方法在第一电介质层之上提供导电栅极层，并且选择性地图案化导电栅极层以在导电栅极层中形成多个孔。 孔的周长和第一孔和第二孔之间的间隔是选择性的，以提供电容器的高品质因数（Q）。 该方法将第二导电类型的杂质通过导电层中的多个孔埋入有源区。 该方法还包括提供第二电介质层和图案化第二电介质层以形成与有源区和栅极的接触。

公开(公告)号：US08722475B2

公开(公告)日：2014-05-13

申请号：US12986123

申请日：2011-01-06

申请人： Zhen Chen ,  Yung Feng Lin

发明人： Zhen Chen ,  Yung Feng Lin

IPC分类号： H01L21/338

CPC分类号： H01L29/93 ,  H01L29/66181 ,  H01L29/94

摘要： A method for forming a variable capacitor includes providing a semiconductor substrate of a first conductivity type and forming an active region of a second conductivity type within the substrate. The method forms a first dielectric layer overlying the active region. The method provides a conductive gate layer over the first dielectric layer and selectively patterns the conductive gate layer to form a plurality of holes in the conductive gate layer. A perimeter of the holes and a spacing between a first and a second holes are selective to provide a high quality factor (Q) of the capacitor. The method implants impurities of the second conductivity type into the active region through the plurality of holes in the conductive layer. The method also includes providing a second dielectric layer and patterning the second dielectric layer to form contacts to the active region and the gate.

摘要翻译： 形成可变电容器的方法包括提供第一导电类型的半导体衬底，并在衬底内形成第二导电类型的有源区。 该方法形成覆盖有源区的第一介电层。 该方法在第一电介质层之上提供导电栅极层，并且选择性地图案化导电栅极层以在导电栅极层中形成多个孔。 孔的周长和第一孔和第二孔之间的间隔是选择性的，以提供电容器的高品质因数（Q）。 该方法将第二导电类型的杂质通过导电层中的多个孔埋入有源区。 该方法还包括提供第二电介质层和图案化第二电介质层以形成与有源区和栅极的接触。

公开(公告)号：US20100157694A1

公开(公告)日：2010-06-24

申请号：US12715504

申请日：2010-03-02

申请人： Jer-Hau Hsu ,  Yung Feng Lin

发明人： Jer-Hau Hsu ,  Yung Feng Lin

IPC分类号： G11C5/14 ,  H03K17/687

CPC分类号： G11C7/12

摘要： A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit. The switch unit includes a clamp transistor having a source, a gate connected to the discharge enhanced bias source, and a drain receiving a voltage; a switch transistor having a gate receiving a control signal, a drain connected to the source of the clamp transistor, and a source connected to a memory array, wherein a parasitic capacitor exists between the gate and the source of the clamp transistor; a resistor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground; and a capacitor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground, wherein a charge in the parasitic capacitor, when the switch transistor is turned on, is almost identical to that when the switch transistor is turned off, so that a couple effect between the switch unit and the discharge enhanced bias source is reduced, thereby stabilizing a bias applied to the memory array.

摘要翻译： 提供了位线电压发生器。 位线电压发生器包括放电增强偏置源和开关单元。 开关单元包括具有源极，连接到放电增强偏置源的栅极和接收电压的漏极的钳位晶体管; 具有接收控制信号的栅极的开关晶体管，连接到钳位晶体管的源极的漏极和连接到存储器阵列的源极，其中寄生电容器存在于钳位晶体管的栅极和源极之间; 电阻器，其具有连接到开关晶体管的漏极的第一端子和连接到地的第二端子; 以及电容器，其具有连接到开关晶体管的漏极的第一端子和连接到地的第二端子，其中当开关晶体管导通时，寄生电容器中的电荷几乎与开关晶体管为 关闭，使得开关单元和放电增强偏置源之间的耦合效应降低，从而稳定施加到存储器阵列的偏置。

公开(公告)号：US07738296B2

公开(公告)日：2010-06-15

申请号：US11955715

申请日：2007-12-13

申请人： Yung Feng Lin

发明人： Yung Feng Lin

IPC分类号： G11C16/06

CPC分类号： G11C16/20 ,  G11C16/04 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0407

摘要： A method for reading data in a nonvolatile memory at a power-on stage is provided and includes the following steps. Firstly, the data are read through a reference voltage. Next, a failure number is counted when reading the data has a fail result. Next, the reference voltage is adjusted when the failure number reaches a predetermined number. The effect effectively and exactly reading configuration information at a power-on stage is accomplished through the method.

摘要翻译： 提供了一种在上电阶段读取非易失性存储器中的数据的方法，包括以下步骤。 首先，通过参考电压读取数据。 接下来，当读取数据具有失败结果时，计数​​失败次数。 接下来，当故障次数达到预定数量时，调整参考电压。 通过该方法实现了在上电阶段有效且准确地读取配置信息的效果。

公开(公告)号：US07786761B2

公开(公告)日：2010-08-31

申请号：US12024404

申请日：2008-02-01

申请人： Yung Feng Lin

发明人： Yung Feng Lin

IPC分类号： H03K19/0175

CPC分类号： H03K19/00361 ,  G11C7/02 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1057 ,  H03K19/0013 ,  H03K19/00384

摘要： A controlling output buffer slew rate method and an output buffer circuit for a memory device is provided. The output buffer include an output stage formed by a PMOS transistor and a NMOS transistor electrically connected in series, a pre-driver for respectively controlling each gate terminal of the PMOS transistor and the NMOS transistor in order to bring these transistors to the turning-on threshold, a first wire, for transmitting a pull-up signal, coupled between the output stage and the pre-driver, and a second wire, for transmitting a pull-down signal, coupled between the output stage and the pre-driver. After a DATA signal transition (logic state is changed from “H” to “L” or “L” from to “H”), the PMOS or NMOS transistor is turned off first, and then the NMOS or PMOS transistor is turned on due to the time difference between the pull-up signal and the pull-down signal.

摘要翻译： 提供了控制输出缓冲器转换速率方法和用于存储器件的输出缓冲器电路。 输出缓冲器包括由PMOS晶体管和串联电连接的NMOS晶体管形成的输出级，用于分别控制PMOS晶体管和NMOS晶体管的每个栅极端子的预驱动器，以便使这些晶体管导通 阈值，用于传输耦合在输出级和预驱动器之间的上拉信号的第一引线和用于传输耦合在输出级和预驱动器之间的下拉信号的第二引线。 在DATA信号转换（逻辑状态从“H”变为“L”或“L”从“H”）开始，PMOS或NMOS晶体管首先关断，然后NMOS或PMOS晶体管导通， 到上拉信号和下拉信号之间的时间差。

公开(公告)号：US20100182834A1

公开(公告)日：2010-07-22

申请号：US12545793

申请日：2009-08-21

申请人： Yung Feng Lin ,  Kuen-Long Chang ,  Chun Hsiung Hung

发明人： Yung Feng Lin ,  Kuen-Long Chang ,  Chun Hsiung Hung

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C7/02

CPC分类号： G11C7/1048 ,  G11C16/28

摘要： Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers.

摘要翻译： 通过使用扭曲的数据线和差分感测放大器来减轻耦合到相邻数据线的非易失性存储器中的数据线上的过度擦除感应噪声。 耦合到数据线中的噪声由耦合到参考数据线中的相似噪声补偿并在差分感测放大器中被消除。