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1.发明授权公开(公告)号：US08644378B2
公开(公告)日：2014-02-04
申请号：US12905265
申请日：2010-10-15
申请人： Zhibing Liu , Jay Liang
发明人： Zhibing Liu , Jay Liang
摘要： A digital video communication device is provided. The digital video communication device includes a transmitter providing a spread-spectrum video signal including a predetermined frequency spread value and a frequency ratio and a receiver receiving the spread-spectrum video signal. The receiver includes a frequency synthesizer, a free-running clock generator configured to generate a free-running clock signal, wherein the free-running clock signal is used as a reference clock signal input to the frequency synthesizer. The receiver further includes a digital control logic circuit configured to separate the frequency ratio from the spread-spectrum video signal, and a line buffer coupled to the digital control logic circuit and the frequency synthesizer, the line buffer adjusting the frequency ratio and sending the adjusted frequency ratio to the frequency synthesizer, wherein the frequency synthesizer combines the free-running clock signal and the adjusted frequency ratio, and outputs a de-spread clock signal.
摘要翻译： 提供数字视频通信设备。 该数字视频通信设备包括一个提供包括预定频率扩展值和频率比的扩频视频信号的发射机和接收扩频视频信号的接收机。 接收机包括频率合成器，自由运行的时钟发生器，被配置为产生自由运行的时钟信号，其中自由运行的时钟信号用作输入到频率合成器的参考时钟信号。 该接收器还包括数字控制逻辑电路，其被配置为将频率比与扩频视频信号分离，并且线缓冲器耦合到数字控制逻辑电路和频率合成器，线路缓冲器调节频率比并发送调整后的 频率合成器，其中频率合成器组合自由运行的时钟信号和调整的频率比，并输出解扩时钟信号。
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2.发明申请SYSTEM AND METHOD FOR CLOCK SELF-ADJUSTMENT IN AUDIO COMMUNICATIONS SYSTEMS 审中-公开用于音频通信系统中时钟自调整的系统和方法公开(公告)号：US20120053709A1
公开(公告)日：2012-03-01
申请号：US12870619
申请日：2010-08-27
申请人： JANE ZHENG , Zhibing Liu , Jay Liang
发明人： JANE ZHENG , Zhibing Liu , Jay Liang
IPC分类号： G06F17/00
CPC分类号： H03L7/183
摘要： System and method for implementing a self-adjusting audio clock in an audio receiver comprising an audio data buffer for buffering data received from a transmitter are described. In one embodiment, the system includes an audio clock recovery circuit for recovering an audio clock signal from a reference clock signal received from the transmitter, wherein the audio clock is provided to the audio data buffer for use in reading data therefrom. The system further includes an adjustment circuit for providing an adjustment signal to the audio clock recovery circuit in accordance with a status of the audio data buffer. Responsive to the status of the audio data buffer indicating that the audio data buffer is approaching overflow, the adjustment signal provided to the audio clock recovery circuit causes an increase in the frequency of the audio clock signal. Responsive to the status of the audio data buffer indicating that the audio data buffer is approaching underflow, the adjustment signal provided to the audio clock recovery circuit causes a decrease in the frequency of the audio clock signal.
摘要翻译： 描述了一种在音频接收机中实现自调节音频时钟的系统和方法，包括用于缓冲从发射机接收的数据的音频数据缓冲器。 在一个实施例中，该系统包括音频时钟恢复电路，用于从从发射机接收的参考时钟信号中恢复音频时钟信号，其中音频时钟被提供给音频数据缓冲器，用于从其读取数据。 该系统还包括调整电路，用于根据音频数据缓冲器的状态向音频时钟恢复电路提供调整信号。 响应于指示音频数据缓冲器正在接近溢出的音频数据缓冲器的状态，提供给音频时钟恢复电路的调整信号导致音频时钟信号的频率的增加。 响应于指示音频数据缓冲器正在下溢的音频数据缓冲器的状态，提供给音频时钟恢复电路的调整信号导致音频时钟信号的频率的降低。
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3.发明授权公开(公告)号：US08135105B2
公开(公告)日：2012-03-13
申请号：US12214288
申请日：2008-06-17
申请人： Zhibing Liu , Sheng-Chiech Liang
发明人： Zhibing Liu , Sheng-Chiech Liang
IPC分类号： H04L7/00
摘要： An output clock correction circuit (14) for correcting a frequency of an output clock in a receiving device (13) that receives data (16) and a time stamp component (18) includes an output clock feedback loop (20), a FIFO buffer (22) and a time stamp adjuster (24). The output clock feedback loop (20) adjusts a phase and/or a frequency of the output clock based at least partially on the time stamp component (18). The FIFO buffer (22) temporarily stores the data (16). The time stamp adjuster (24) selectively adjusts the time stamp component (18) based on a status of the FIFO buffer (22). In one embodiment, the status is based at least in part on an actual data level in the FIFO buffer (22). In another embodiment, the FIFO buffer (22) has a target data level range, and the time stamp adjuster (24) adjusts the time stamp component (18) when the actual data level in the FIFO buffer (22) is outside this range. The time stamp adjuster (24) can adjust the time stamp component (18) by an amount that is based on a calculation, or an amount that is determined from a lookup table.
摘要翻译： 一种用于校正接收数据（16）和时间戳分量（18）的接收装置（13）中的输出时钟的频率的输出时钟校正电路（14），包括输出时钟反馈回路（20），FIFO缓冲器 （22）和时间戳调整器（24）。 输出时钟反馈回路（20）至少部分地基于时间戳组件（18）来调整输出时钟的相位和/或频率。 FIFO缓冲器（22）临时存储数据（16）。 时间戳调整器（24）基于FIFO缓冲器（22）的状态选择性地调整时间戳分量（18）。 在一个实施例中，状态至少部分地基于FIFO缓冲器（22）中的实际数据电平。 在另一实施例中，FIFO缓冲器（22）具有目标数据电平范围，并且当FIFO缓冲器（22）中的实际数据电平在该范围之外时，时间戳调整器（24）调整时间戳分量（18）。 时间戳调整器（24）可以基于计算的量或从查找表确定的量来调整时间戳组件（18）。
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4.发明申请公开(公告)号：US20090310729A1
公开(公告)日：2009-12-17
申请号：US12214288
申请日：2008-06-17
申请人： Zhibing Liu , Sheng-Chiech Liang
发明人： Zhibing Liu , Sheng-Chiech Liang
IPC分类号： H04L7/00
摘要： An output clock correction circuit (14) for correcting a frequency of an output clock in a receiving device (13) that receives data (16) and a time stamp component (18) includes an output clock feedback loop (20), a FIFO buffer (22) and a time stamp adjuster (24). The output clock feedback loop (20) adjusts a phase and/or a frequency of the output clock based at least partially on the time stamp component (18). The FIFO buffer (22) temporarily stores the data (16). The time stamp adjuster (24) selectively adjusts the time stamp component (18) based on a status of the FIFO buffer (22). In one embodiment, the status is based at least in part on an actual data level in the FIFO buffer (22). In another embodiment, the FIFO buffer (22) has a target data level range, and the time stamp adjuster (24) adjusts the time stamp component (18) when the actual data level in the FIFO buffer (22) is outside this range. The time stamp adjuster (24) can adjust the time stamp component (18) by an amount that is based on a calculation, or an amount that is determined from a lookup table.
摘要翻译： 一种用于校正接收数据（16）和时间戳分量（18）的接收装置（13）中的输出时钟的频率的输出时钟校正电路（14），包括输出时钟反馈回路（20），FIFO缓冲器 （22）和时间戳调整器（24）。 输出时钟反馈回路（20）至少部分地基于时间戳组件（18）来调整输出时钟的相位和/或频率。 FIFO缓冲器（22）临时存储数据（16）。 时间戳调整器（24）基于FIFO缓冲器（22）的状态选择性地调整时间戳分量（18）。 在一个实施例中，状态至少部分地基于FIFO缓冲器（22）中的实际数据电平。 在另一实施例中，FIFO缓冲器（22）具有目标数据电平范围，并且当FIFO缓冲器（22）中的实际数据电平在该范围之外时，时间戳调整器（24）调整时间戳分量（18）。 时间戳调整器（24）可以基于计算的量或从查找表确定的量来调整时间戳组件（18）。
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5.发明授权公开(公告)号：US08326547B2
公开(公告)日：2012-12-04
申请号：US12894401
申请日：2010-09-30
申请人： Xiaowu Liu , Yun He , Zhuying Wang , Chunjiao Wang , Zhibing Liu , Tianhui Xia , Luquan Wang , Fang Liang Zhang
发明人： Xiaowu Liu , Yun He , Zhuying Wang , Chunjiao Wang , Zhibing Liu , Tianhui Xia , Luquan Wang , Fang Liang Zhang
摘要： An improved gene sequence optimization method, the systematic optimization method, is described for boosting the recombinant expression of genes in bacteria, yeast, insect and mammalian cells. This general method takes into account of multiple, preferably most or all, of the parameters and factors affecting protein expression including codon usage, tRNA usage, GC-content, ribosome binding sequences, promoter, 5′-UTR, ORF and 3′-UTR sequences of the genes to improve and optimize the gene sequences to boost the protein expression of the genes in bacteria, yeast, insect and mammalian cells. In particular, the invention relates to a system and a method for sequence optimization for improved recombinant protein expression using a particle swarm optimization algorithm. The improved systematic optimization method can be incorporated into a software for more efficient optimization.
摘要翻译： 描述了改进的基因序列优化方法，该系统优化方法用于增强细菌，酵母，昆虫和哺乳动物细胞中基因的重组表达。 这种一般方法考虑了影响蛋白质表达的参数和因子的多个，优选大多数或全部，包括密码子使用，tRNA使用，GC含量，核糖体结合序列，启动子，5'-UTR，ORF和3'-UTR 改进和优化基因序列以增强细菌，酵母，昆虫和哺乳动物细胞中基因的蛋白质表达的基因序列。 特别地，本发明涉及使用粒子群优化算法改进重组蛋白表达的序列优化的系统和方法。 改进的系统优化方法可以被并入软件中以进行更有效的优化。
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