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    System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing
    1.
    发明授权
    System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing 有权
    使用横向PNP或PMOS或两者用于衬底偏置的静电放电保护的系统和方法

    公开(公告)号：US06628493B1

    公开(公告)日：2003-09-30

    申请号：US09546988

    申请日：2000-04-11

    申请人： Zhiliang Julian Chen ,  Thomas A. Vrotsos ,  E. Ajith Amerasekera

    发明人： Zhiliang Julian Chen ,  Thomas A. Vrotsos ,  E. Ajith Amerasekera

    IPC分类号： H02H900

    CPC分类号： H01L27/027 ,  H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit (10) comprising at least one input element (20) is protected by a protective circuit (40). The protective circuit (40) is operable to protect the integrated circuit (10) from damage due to electrostatic discharge and may be coupled to the input element (20). The protective circuit (40) comprises a lateral NPN transistor (T1) coupled to the input element (20) and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element (20). The protective circuit (40) also may comprise a lateral PNP transistor (T2) coupled to the input element (20) and to the lateral NPN transistor (T1). The lateral PNP transistor (T2) is operable to aid in raising a potential of the base of the lateral NPN transistor (T1). Alternatively, the protective circuit (40) also may use a PMOS traisistor (P1), or a PMOS transistor (P1) in combination with the lateral NPN transistor (T1), coupled to the input element (20) and to the lateral NPN transistor (T1). The PMOS transistor (P1) is operable to aid in raising the potential of the base of the lateral NPN transistor (T1).

    摘要翻译： 本发明包括提供静电放电保护的系统和方法。 在本发明的一个实施例中，包括至少一个输入元件（20）的集成电路（10）由保护电路（40）保护。 保护电路（40）可操作以保护集成电路（10）免受静电放电所造成的损坏，并可与输入元件（20）耦合。 保护电路（40）包括耦合到输入元件（20）的横向NPN晶体管（T1），并且可操作以在输入元件电压超过阈值时启动，阈值大于或等于耦合到该电路的电路的正常工作电压 输入元件（20）。 保护电路（40）还可以包括耦合到输入元件（20）和横向NPN晶体管（T1）的横向PNP晶体管（T2）。 横向PNP晶体管（T2）可操作以帮助提高横向NPN晶体管（T1）的基极的电位。 或者，保护电路（40）还可以使用与横向NPN晶体管（T1）组合的PMOS晶体管（P1）或PMOS晶体管（P1），耦合到输入元件（20）和横向NPN晶体管 （T1）。 PMOS晶体管（P1）可操作以帮助提高横向NPN晶体管（T1）的基极的电位。

    System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing
    2.
    发明授权
    System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing 有权
    使用横向PNP或PMOS或两者用于衬底偏置的静电放电保护的系统和方法

    公开(公告)号：US06873506B2

    公开(公告)日：2005-03-29

    申请号：US10655865

    申请日：2003-09-05

    申请人： Zhiliang Julian Chen ,  Thomas A. Vrotsos ,  Ajith E. Amerasekera

    发明人： Zhiliang Julian Chen ,  Thomas A. Vrotsos ,  Ajith E. Amerasekera

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H02H9/00

    CPC分类号： H01L27/027 ,  H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit (10) comprising at least one input element (20) is protected by a protective circuit (40). The protective circuit (40) is operable to protect the integrated circuit (10) from damage due to electrostatic discharge and may be coupled to the input element (20). The protective circuit (40) comprises a lateral NPN transistor (T1) coupled to the input element (20) and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element (20). The protective circuit (40) also may comprise a lateral PNP transistor (T2) coupled to the input element (20) and to the lateral NPN transistor (T1). The lateral PNP transistor (T2) is operable to aid in raising a potential of the base of the lateral NPN transistor (T1). Alternatively, the protective circuit (40) also may use a PMOS transistor (P1), or a PMOS transistor (P1) in combination with the lateral NPN transistor (T1), coupled to the input element (20) and to the lateral NPN transistor (T1). The PMOS transistor (P1) is operable to aid in raising the potential of the base of the lateral NPN transistor (T1).

    摘要翻译： 本发明包括提供静电放电保护的系统和方法。 在本发明的一个实施例中，包括至少一个输入元件（20）的集成电路（10）由保护电路（40）保护。 保护电路（40）可操作以保护集成电路（10）免受静电放电所造成的损坏，并可与输入元件（20）耦合。 保护电路（40）包括耦合到输入元件（20）的横向NPN晶体管（T1），并且可操作以在输入元件电压超过阈值时启动，阈值大于或等于耦合到该电路的电路的正常工作电压 输入元件（20）。 保护电路（40）还可以包括耦合到输入元件（20）和横向NPN晶体管（T1）的横向PNP晶体管（T2）。 横向PNP晶体管（T2）可操作以帮助提高横向NPN晶体管（T1）的基极的电位。 或者，保护电路（40）还可以使用PMOS晶体管（P1）或与横向NPN晶体管（T1）组合的PMOS晶体管（P1），耦合到输入元件（20）和横向NPN晶体管 （T1）。 PMOS晶体管（P1）可操作以帮助提高横向NPN晶体管（T1）的基极的电位。

    CMOS imager having asynchronous pixel readout in order of pixel illumination
    3.
    发明授权
    CMOS imager having asynchronous pixel readout in order of pixel illumination 有权
    CMOS成像器具有像素照明顺序的异步像素读出

    公开(公告)号：US06660989B2

    公开(公告)日：2003-12-09

    申请号：US10190785

    申请日：2002-07-08

    申请人： Xiaochuan Guo ,  Zhiliang Julian Chen ,  John G. Harris

    发明人： Xiaochuan Guo ,  Zhiliang Julian Chen ,  John G. Harris

    IPC分类号： H04N5335

    CPC分类号： H04N5/341

    摘要： This CMOS imager represents illuminance in the time domain. Once per frame, each pixel outputs a pulse after a time proportional to the illuminance on that pixel. Therefore, the illuminance on that pixel is related to the time difference between its pulse event and global reset of the imager. A counter reports the times of these pulse events in a digital format. Thus no analog to digital converter is necessary. This imager enables easy computation of pixel intensity histograms. Frame data is stored in pixel intensity order using row and column arbiters to produce a pixel address. Because each pixel has its own exposure time, the imager has a wide dynamic range of 120 dB. This imager has low power dissipation and avoids the noise and mismatch problems of prior complicated analog readout circuits.

    摘要翻译： 该CMOS成像器表示时域中的照度。 每帧一次，每个像素在与该像素上的照度成比例的时间之后输出脉冲。 因此，该像素的照度与其脉冲事件与成像器的全局复位之间的时间差有关。 计数器以数字格式报告这些脉冲事件的时间。 因此，不需要模数转换器。 该成像器能够容易地计算像素强度直方图。 帧数据使用行和列仲裁器以像素强度顺序存储以产生像素地址。 因为每个像素都有自己的曝光时间，所以成像器具有120 dB的宽动态范围。 该成像器具有低功耗，并避免了以前复杂的模拟读出电路的噪声和失配问题。

    System and method to facilitate time domain sampling for solid state imager
    6.
    发明授权
    System and method to facilitate time domain sampling for solid state imager 有权
    用于固态成像仪的时域采样的系统和方法

    公开(公告)号：US07474345B2

    公开(公告)日：2009-01-06

    申请号：US10217581

    申请日：2002-08-12

    申请人： Qiang Luo ,  Zhiliang Julian Chen ,  John G. Harris ,  Steve Clynes ,  Michael Erwin

    发明人： Qiang Luo ,  Zhiliang Julian Chen ,  John G. Harris ,  Steve Clynes ,  Michael Erwin

    IPC分类号： H04N3/14 ,  H04N5/335

    CPC分类号： H04N5/335

    摘要： A time domain sampling technique for a CMOS imager enables a wide dynamic range and flexibility by employing up to two-degrees of freedom during such sampling. Two degrees of freedom can be achieved by making one or both of an integration time and a reference (e.g., voltage or current) variable during sampling. The sampling (or image capture) is implemented by associating a time with when a pixel has a desired value relative to the reference in response to the pixel receiving incident light. The reference can be fixed or variable during different portions of the sampling, and further can be programmable to implement a desired sampling pattern for a given application.

    摘要翻译： CMOS成像器的时域采样技术可以在这种采样过程中采用高达两个自由度的宽动态范围和灵活性。 通过在采样期间通过使积分时间和参考（例如，电压或电流）变量中的一个或两个可以实现两个自由度。 采样（或图像捕获）是通过将时间与当像素具有相对于基准的期望值相对应于像素接收入射光而相关联来实现的。 参考在采样的不同部分期间可以是固定的或可变的，并且还可以被编程以实现给定应用的期望的采样模式。

    Defective pixel filtering for digital imagers
    7.
    发明授权
    Defective pixel filtering for digital imagers 有权
    数字成像器的缺陷像素滤波

    公开(公告)号：US07286179B2

    公开(公告)日：2007-10-23

    申请号：US10798211

    申请日：2004-03-10

    申请人： Zhiliang Julian Chen ,  Eugene G. Dierschke ,  Steven Derek Clynes ,  Anli Liu

    发明人： Zhiliang Julian Chen ,  Eugene G. Dierschke ,  Steven Derek Clynes ,  Anli Liu

    IPC分类号： H04N9/64

    CPC分类号： H04N5/3675 ,  H04N5/16 ,  H04N5/20 ,  H04N5/243

    摘要： Defective pixels in a CMOS array give rise to spot noise that diminishes the integrity of the resulting image. Because CMOS arrays and digital logic can be fabricated on the same integrated circuit using the same processing technology and relatively inexpensive and fast circuit can be employed to digitally filter the pixel data stream and to identify pixels having values that do not fall in the range defined by the immediately neighboring pixels and the deviate from the neighboring pixels by more than a threshold amount. Such conditions would indicate that the deviation is caused by a defective pixel rather than by desired image data. The threshold amount can be preprogrammed or can be provided by a user or can be dynamically set using feedback indicating image quality. The filter would also provide a solution for other sensors such as CCD, although a single chip solution would likely not be possible.

    摘要翻译： CMOS阵列中的不良像素会产生斑点噪声，从而降低所得图像的完整性。 由于可以使用相同的处理技术在相同的集成电路上制造CMOS阵列和数字逻辑，并且可以使用相对便宜且快速的电路来对像素数据流进行数字滤波，并且识别具有不在下面限定的范围内的值的像素 紧邻相邻像素并且偏离相邻像素超过阈值量。 这样的条件将指示偏差是由缺陷像素而不是期望的图像数据引起的。 阈值可以是预编程的，也可以由用户提供，也可以使用表示图像质量的反馈进行动态设定。 该滤波器还将为其他传感器（如CCD）提供解决方案，尽管单芯片解决方案可能无法实现。

    System and method of dual mode automatic gain control for a digital radio receiver
    8.
    发明授权
    System and method of dual mode automatic gain control for a digital radio receiver 有权
    用于数字无线电接收机的双模式自动增益控制系统和方法

    公开(公告)号：US06831957B2

    公开(公告)日：2004-12-14

    申请号：US09805825

    申请日：2001-03-14

    申请人： Zhiliang Julian Chen

    发明人： Zhiliang Julian Chen

    IPC分类号： H04L2708

    CPC分类号： H03G3/002 ,  H03G3/3089 ,  H04H2201/20

    摘要： A digital radio receiver system uses a dual mode automatic gain control architecture and method to enhance signal-to-noise ratio and linearity to accommodate reception and processing of both L-band RF signals and band-III RF signals. The system architecture employs an analog AGC to control high/low gain switches associated with front end low noise amplifiers and down converters, as well as a digital AGC to control gain controlled amplifier and programmable gain amplifier gain settings. The AGC control can be implemented totally within the system architecture or optionally can be implemented via an external data processing device such as a DSP or micro-controller.

    摘要翻译： 数字无线电接收机系统使用双模式自动增益控制架构和方法来增强信噪比和线性度，以适应L波段RF信号和频带III射频信号的接收和处理。 系统架构采用模拟AGC来控制与前端低噪声放大器和下变频器相关的高/低增益开关，以及用于控制增益控制放大器和可编程增益放大器增益设置的数字AGC。 AGC控制可以在系统架构内完全实现，或者可以通过诸如DSP或微控制器的外部数据处理设备来实现。

    Digital imaging control with selective intensity resolution enhancement
    9.
    发明授权
    Digital imaging control with selective intensity resolution enhancement 有权
    具有选择性强度分辨率增强的数字成像控制

    公开(公告)号：US06788340B1

    公开(公告)日：2004-09-07

    申请号：US09475901

    申请日：1999-12-30

    申请人： Zhiliang Julian Chen ,  Eugene G. Dierschke ,  Steven Derek Clynes ,  Anli Liu

    发明人： Zhiliang Julian Chen ,  Eugene G. Dierschke ,  Steven Derek Clynes ,  Anli Liu

    IPC分类号： H04N5235

    CPC分类号： H04N5/243 ,  H04N5/20 ,  H04N5/367

    摘要： Image enhancement is automatically achieved by calibrating the reference voltage and gain of a differential amplifier and the integration interval so as to provide an input to a differential analog to digital converter (ADC) that utilizes the full dynamic range of the ADC. When used with a CMOS array, the imaging logic can be fabricated on a single chip with the array using combinational logic for fast, inexpensive calibration. Another advantageous feature is the ability to expand a desired portion of the luminance spectrum of the image in order to increase the digital resolution of the resulting image for that portion of the spectrum of interest.

    摘要翻译： 通过校准差分放大器的参考电压和增益以及积分间隔来自动实现图像增强，从而为使用ADC的全动态范围的差分模数转换器（ADC）提供输入。 当与CMOS阵列一起使用时，可以使用组合逻辑在单个芯片上制造成像逻辑，以实现快速，便宜的校准。 另一个有利的特征是能够扩展图像的亮度谱的期望部分，以便增加对于感兴趣的频谱部分的所得图像的数字分辨率。