公开(公告)号：US09041203B2

公开(公告)日：2015-05-26

申请号：US12249261

申请日：2008-10-10

申请人： Zubin Patel ,  Nian Yang ,  Fan Wan Lai ,  Alok Nandini Roy

发明人： Zubin Patel ,  Nian Yang ,  Fan Wan Lai ,  Alok Nandini Roy

IPC分类号： H01L23/38 ,  H01L23/522

CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for manufacturing a semiconductor device including multi-layer bitlines. The location of the bitlines in multiple layers provides for increased spacing and increased width thereby overcoming the limitations of the pitch dictated by the semiconductor fabrication process used. The bitlines locations in multiple layers thus allows the customization of the spacing and width according to the use of a semiconductor device.

摘要翻译： 一种用于制造包括多层位线的半导体器件的系统和方法。 位线在多层中的位置提供了增加的间隔和增加的宽度，从而克服了由所使用的半导体制造工艺所规定的间距的限制。 因此，根据半导体器件的使用，多层中的位线位置允许定制间隔和宽度。

公开(公告)号：US08560756B2

公开(公告)日：2013-10-15

申请号：US11873810

申请日：2007-10-17

申请人： Nian Yang ,  Jiang Li ,  Fan Wan Lai

发明人： Nian Yang ,  Jiang Li ,  Fan Wan Lai

IPC分类号： G06F12/00

CPC分类号： G06F12/0638 ,  G11C11/005 ,  G11C16/0408

摘要： A hybrid memory system is provided that combines the advantages of NAND flash memory devices with the advantages of NOR flashes memory devices. The system includes a NAND flash memory portion to provide mass storage and fast programming/erasure capabilities of conventional NAND flash memory devices. The system further comprises a NOR flash memory portion to provide code storage and fast random reading capabilities of conventional NOR flash memory devices. Accordingly, the hybrid memory system provides both mass storage and code storage along with fast programming/erasure speeds and fast random access speeds.

摘要翻译： 提供了混合存储器系统，其结合NAND闪存器件的优点与NOR闪存存储器件的优点。 该系统包括NAND闪速存储器部分，用于提供大容量存储和传统NAND闪速存储器件的快速编程/擦除能力。 该系统还包括NOR闪速存储器部分，以提供常规NOR闪存器件的代码存储和快速随机读取能力。 因此，混合存储器系统同时提供大容量存储和代码存储以及快速编程/擦除速度和快速随机存取速度。

公开(公告)号：US20090273998A1

公开(公告)日：2009-11-05

申请号：US12114966

申请日：2008-05-05

申请人： Hongtau Mu ,  Nian Yang ,  Fan Wan Lai ,  Guowei Wang

发明人： Hongtau Mu ,  Nian Yang ,  Fan Wan Lai ,  Guowei Wang

IPC分类号： G11C7/06

CPC分类号： G11C7/067 ,  G11C7/062 ,  G11C7/08 ,  G11C2207/063

摘要： A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved.

摘要翻译： 存储器件包括用于感测位单元的状态的读出放大器。 读出放大器包括通过开关连接的两个输入端。 一个输入端子连接到一个节点，由此通过该节点的电流表示由位单元和参考电流所画出的电流差。 在第一阶段期间，读出放大器的输入端之间的开关闭合，使得两个输入端施加公共电压。 在第二阶段期间，开关被打开，并且感测放大器基于通过节点的电流来感测存储在位单元的信息的状态。 通过使用开关来连接和断开两相中的读出放大器的输入，可以确定存储在位单元中的信息的状态的精度和速度。

公开(公告)号：US20080130371A1

公开(公告)日：2008-06-05

申请号：US11950811

申请日：2007-12-05

申请人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

发明人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC分类号： G11C16/12 ,  G11C16/28

CPC分类号： G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

公开(公告)号：US07804715B2

公开(公告)日：2010-09-28

申请号：US12114966

申请日：2008-05-05

申请人： Hongtau Mu ,  Nian Yang ,  Fan Wan Lai ,  Guowei Wang

发明人： Hongtau Mu ,  Nian Yang ,  Fan Wan Lai ,  Guowei Wang

IPC分类号： G11C16/06

CPC分类号： G11C7/067 ,  G11C7/062 ,  G11C7/08 ,  G11C2207/063

摘要： A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved.

摘要翻译： 存储器件包括用于感测位单元的状态的读出放大器。 读出放大器包括通过开关连接的两个输入端。 一个输入端子连接到一个节点，由此通过该节点的电流表示由位单元和参考电流所画出的电流差。 在第一阶段期间，读出放大器的输入端之间的开关闭合，使得两个输入端施加公共电压。 在第二阶段期间，开关被打开，并且感测放大器基于通过节点的电流来感测存储在位单元的信息的状态。 通过使用开关来连接和断开两相中的读出放大器的输入，可以确定存储在位单元中的信息的状态的精度和速度。

公开(公告)号：US07345916B2

公开(公告)日：2008-03-18

申请号：US11423638

申请日：2006-06-12

申请人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

发明人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C5/14 ,  G11C7/00

CPC分类号： G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200).For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

公开(公告)号：US20070291550A1

公开(公告)日：2007-12-20

申请号：US11423638

申请日：2006-06-12

申请人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

发明人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C8/00 ,  G11C7/00 ,  G11C16/06

CPC分类号： G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200).For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

公开(公告)号：US07613044B2

公开(公告)日：2009-11-03

申请号：US11950811

申请日：2007-12-05

申请人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

发明人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C7/10

CPC分类号： G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

摘要翻译： 提供了一种用于在半导体存储器件（100）的选定存储单元（200）上进行高性能，高电压存储器操作的方法和装置。 在编程或擦除操作期间，高电压发生器（106）在所选择的字线（502）上提供连续的高电压电平（702），并且向位线解码器（120）保持连续的高电压电平供应，位线解码器（120）依次提供高电压 电平（706）到位线（504）的第一部分，并且在将高电压电平提供给第二部分（710）之前对那些位线（504）进行放电（708）。 为了对编程操作进一步改进，高电压发生器（106）通过在其间提供电流控制装置（1208）来解耦提供给字线（502）和位线（504）的高电压，并在 时间（1104）以克服由与所选位线（504）和/或位线解码器（120）相关联的电容器负载导致的电压电平下降（1102），所述位线（504）的第二部分预充电（1716） 同时向第一部分提供高电压电平以对存储单元（200）的第一部分进行编程（1706）。 为了改进读取操作，动态参考单元（2002）是空白的是通过从第一电压源（2112）到动态参考单元（2002）和从第二电压源（2104）提供非相同调节的高电压电平来确定的 ）到静态参考单元（2004），并且如果动态参考单元（2002）不为空白，则通过向所选择的存储单元（200），动态参考单元（200）提供相同调节的高电压电平来读取所选存储单元（200） 2002）和静态参考单元（2004）。

公开(公告)号：US07532518B2

公开(公告)日：2009-05-12

申请号：US11767622

申请日：2007-06-25

申请人： Nian Yang ,  Fan Wan Lai ,  Aaron Lee

发明人： Nian Yang ,  Fan Wan Lai ,  Aaron Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/30 ,  G11C16/10

摘要： Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their location, which can in turn cause non-uniformity in the speed of high voltage operations on the memory array such as programming. The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell. For example, a compensated operation voltage can be provided that is higher near the center of the memory array and lower near an edge of the memory array, thereby lessening the effect of distributed substrate resistance and providing increased operation speed uniformity throughout the memory array.

摘要翻译： 本文提供的系统和方法用于提高闪存设备中的操作速度均匀性。 由于典型的闪存阵列的特征，存储器阵列中的存储器单元可能经历分布式衬底电阻，随着存储器单元与存储器阵列的边缘的距离增加而增加。 分布式基板电阻的这种差异可以根据其位置改变提供给存储器阵列中的不同存储单元的电压，这进而导致存储器阵列上的高电压操作的速度（例如编程）的不一致。 本文提供的系统和方法通过至少部分地基于每个相应存储器单元的位置，通过向存储器阵列中的存储器单元提供补偿的电压电平来降低操作速度的不均匀性。 例如，可以提供补偿操作电压，其在存储器阵列的中心附近较高，并且在存储器阵列的边缘附近较低，从而减小分布式衬底电阻的影响并且提供整个存储器阵列中的增加的操作速度均匀性。

公开(公告)号：US20080316830A1

公开(公告)日：2008-12-25

申请号：US11767622

申请日：2007-06-25

申请人： Nian Yang ,  Fan Wan Lai ,  Aaron Lee

发明人： Nian Yang ,  Fan Wan Lai ,  Aaron Lee

IPC分类号： G11C7/00

CPC分类号： G11C16/30 ,  G11C16/10

摘要： Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their location, which can in turn cause non-uniformity in the speed of high voltage operations on the memory array such as programming. The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell. For example, a compensated operation voltage can be provided that is higher near the center of the memory array and lower near an edge of the memory array, thereby lessening the effect of distributed substrate resistance and providing increased operation speed uniformity throughout the memory array.

摘要翻译： 本文提供的系统和方法用于提高闪存设备中的操作速度均匀性。 由于典型的闪存阵列的特征，存储器阵列中的存储器单元可能经历分布式衬底电阻，随着存储器单元与存储器阵列的边缘的距离增加而增加。 分布式基板电阻的这种差异可以根据其位置改变提供给存储器阵列中的不同存储单元的电压，这进而导致存储器阵列上的高电压操作的速度（例如编程）的不一致。 本文提供的系统和方法通过至少部分地基于每个相应存储器单元的位置，通过向存储器阵列中的存储器单元提供补偿的电压电平来降低操作速度的不均匀性。 例如，可以提供补偿操作电压，其在存储器阵列的中心附近较高，并且在存储器阵列的边缘附近较低，从而减小分布式衬底电阻的影响并且提供整个存储器阵列中的增加的操作速度均匀性。