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公开(公告)号：US10714201B2
公开(公告)日：2020-07-14
申请号：US16573998
申请日：2019-09-17
发明人： Chieh-Tse Lee , Chun-Hung Lin , Cheng-Da Huang
摘要： A memory system includes a plurality of memory cells. A memory cell includes an anti-fuse transistor, a first select unit, and a second select unit. The anti-fuse transistor has a first terminal, a second terminal, and a control terminal coupled to an anti-fuse control line. The first select unit is coupled to the first terminal of the anti-fuse transistor, a first bit line, and an odd word line. The second select unit is coupled to the second terminal of the anti-fuse transistor, a second bit line, and an even word line. During a pre-screen operation of the memory cell, the odd word line and the even word line are at different voltages.
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公开(公告)号：US20220199178A1
公开(公告)日：2022-06-23
申请号：US17469828
申请日：2021-09-08
发明人： Chieh-Tse Lee , Ting-Yang Yen , Cheng-Da Huang , Chun-Hung Lin
摘要： When a driving circuit of an anti-fuse memory device programs a selected anti-fuse memory cell, voltage differences between unselected bit lines and unselected anti-fuse control lines would be eliminated or decreased to an acceptable value by floating unselected anti-fuse control lines or by applying a second control line voltage to the unselected anti-fuse control lines. Leakage currents flowing from unselected bit lines through ruptured anti-fuse transistors of the anti-fuse memory device to the unselected anti-fuse control lines would be decreased or eliminated, and program disturbance would be avoided.
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公开(公告)号：US10176883B2
公开(公告)日：2019-01-08
申请号：US15402242
申请日：2017-01-10
发明人： Chieh-Tse Lee , Chih-Chun Chen , Cheng-Da Huang , Chun-Hung Lin
IPC分类号： G06F3/06 , G11C5/06 , G11C17/18 , G11C17/16 , H04L9/32 , G11C29/00 , G11C16/22 , G11C7/24 , G06F21/73 , G11C16/04 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/32 , G06F11/10 , G06F21/72 , H03K3/356 , G11C7/10 , G11C7/22 , G06F12/14 , H01L27/112
摘要： A power-up sequence protection circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. First terminals of the first transistor, the second transistor, and the fourth transistor are coupled for receiving a program voltage. A control terminal of the third transistor is used for receiving a device voltage. A second terminal of the fourth transistor is used for outputting the program voltage when the fourth transistor is turned on. When the program voltage is unexpectedly powered up while the device voltage is not powered up, the first transistor is turned on, the second transistor is turned off, and the fourth transistor is turned off so as to block the program voltage outputted from the second terminal of the fourth transistor.
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公开(公告)号：US20170207773A1
公开(公告)日：2017-07-20
申请号：US15402242
申请日：2017-01-10
发明人： Chieh-Tse Lee , Chih-Chun Chen , Cheng-Da Huang , Chun-Hung Lin
IPC分类号： H03K3/356
CPC分类号： G11C17/18 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/1076 , G06F12/1408 , G06F21/72 , G06F21/73 , G06F2212/1052 , G06F2212/402 , G11C5/063 , G11C7/10 , G11C7/22 , G11C7/24 , G11C16/0408 , G11C16/08 , G11C16/22 , G11C16/24 , G11C16/26 , G11C16/32 , G11C17/16 , G11C29/785 , H01L27/11206 , H03K3/356113 , H04L9/3278
摘要： A power-up sequence protection circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. First terminals of the first transistor, the second transistor, and the fourth transistor are coupled for receiving a program voltage. A control terminal of the third transistor is used for receiving a device voltage. A second terminal of the fourth transistor is used for outputting the program voltage when the fourth transistor is turned on. When the program voltage is unexpectedly powered up while the device voltage is not powered up, the first transistor is turned on, the second transistor is turned off, and the fourth transistor is turned off so as to block the program voltage outputted from the second terminal of the fourth transistor.
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公开(公告)号：US11783905B2
公开(公告)日：2023-10-10
申请号：US17469828
申请日：2021-09-08
发明人： Chieh-Tse Lee , Ting-Yang Yen , Cheng-Da Huang , Chun-Hung Lin
摘要： When a driving circuit of an anti-fuse memory device programs a selected anti-fuse memory cell, voltage differences between unselected bit lines and unselected anti-fuse control lines would be eliminated or decreased to an acceptable value by floating unselected anti-fuse control lines or by applying a second control line voltage to the unselected anti-fuse control lines. Leakage currents flowing from unselected bit lines through ruptured anti-fuse transistors of the anti-fuse memory device to the unselected anti-fuse control lines would be decreased or eliminated, and program disturbance would be avoided.
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公开(公告)号：US20200126630A1
公开(公告)日：2020-04-23
申请号：US16573998
申请日：2019-09-17
发明人： Chieh-Tse Lee , Chun-Hung Lin , Cheng-Da Huang
摘要： A memory system includes a plurality of memory cells. A memory cell includes an anti-fuse transistor, a first select unit, and a second select unit. The anti-fuse transistor has a first terminal, a second terminal, and a control terminal coupled to an anti-fuse control line. The first select unit is coupled to the first terminal of the anti-fuse transistor, a first bit line, and an odd word line. The second select unit is coupled to the second terminal of the anti-fuse transistor, a second bit line, and an even word line. During a pre-screen operation of the memory cell, the odd word line and the even word line are at different voltages.
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