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公开(公告)号：US10714201B2
公开(公告)日：2020-07-14
申请号：US16573998
申请日：2019-09-17
发明人： Chieh-Tse Lee , Chun-Hung Lin , Cheng-Da Huang
摘要： A memory system includes a plurality of memory cells. A memory cell includes an anti-fuse transistor, a first select unit, and a second select unit. The anti-fuse transistor has a first terminal, a second terminal, and a control terminal coupled to an anti-fuse control line. The first select unit is coupled to the first terminal of the anti-fuse transistor, a first bit line, and an odd word line. The second select unit is coupled to the second terminal of the anti-fuse transistor, a second bit line, and an even word line. During a pre-screen operation of the memory cell, the odd word line and the even word line are at different voltages.
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公开(公告)号：US10700080B2
公开(公告)日：2020-06-30
申请号：US16513740
申请日：2019-07-17
发明人： Chien-Han Wu , Chun-Hung Lu , Chun-Hung Lin , Cheng-Da Huang
IPC分类号： G11C7/00 , H01L27/11558 , H03K3/012 , G11C14/00 , H01L29/10 , H01L27/11524 , G11C16/04 , G11C16/14 , G11C16/26 , G11C16/10 , H01L29/49 , H03K19/0185 , H03K19/20 , H03K3/037 , G11C11/419 , G11C13/00 , G11C7/24 , G11C11/16 , G11C17/16
摘要： A random bit cell includes a random bit cell. The random bit cell includes a volatile memory unit, a first non-volatile memory unit, a second non-volatile memory unit, a first select transistor, and a second select transistor. The first non-volatile memory unit is coupled to a first data terminal of the volatile memory unit, and the second non-volatile memory unit is coupled to a second data terminal of the volatile memory unit. The first select transistor has a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line. The second select transistor has a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to a word line.
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公开(公告)号：US10410697B2
公开(公告)日：2019-09-10
申请号：US15942837
申请日：2018-04-02
发明人： Chih-Chun Chen , Chun-Hung Lin , Cheng-Da Huang
IPC分类号： G11C16/26 , G11C16/04 , G11C16/32 , G11C11/56 , G11C7/22 , H01L27/06 , H01L27/112 , G06F21/73 , G11C7/06 , G11C7/12 , G11C7/24 , G11C17/16 , G11C17/18 , G11C16/34 , G11C29/44 , G11C16/08 , G11C16/24 , H02H9/04 , G06F7/00 , H04L9/08 , G11C16/06 , G11C16/10 , G11C16/14
摘要： A sensing circuit includes a sensing stage. The sensing stage includes a voltage clamp, a P-type transistor and an N-type transistor. The voltage clamp receives a first power supply voltage and generates a second power supply voltage. The source terminal of the P-type transistor receives the second power supply voltage. The gate terminal of the P-type transistor receives a cell current from a selected circuit of a non-volatile memory. The drain terminal of the N-type transistor is connected with the drain terminal of the P-type transistor. The gate terminal of the N-type transistor receives a bias voltage. The source terminal of the N-type transistor receives a ground voltage. In a sensing period, the second power supply voltage from the voltage clamp is fixed and lower than the first power supply voltage.
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公开(公告)号：US09214203B2
公开(公告)日：2015-12-15
申请号：US14178277
申请日：2014-02-12
发明人： Po-Ping Wang , Cheng-Da Huang , Chun-Hung Lin
摘要： A sensing apparatus and data sensing method are provided. The sensing apparatus includes an initial circuit, a reference current generator and a sensing circuit. The initial circuit discharges a sensing end to a reference ground during a discharge period, and pre-charges the sensing end to a preset voltage level during a pre-charge period according to an output signal. The reference current generator draws a reference current from the sensing end. The sensing circuit senses a voltage level on the sensing end to generate the output signal. Wherein, the sensing end receives a cell current from a memory cell, and the pre-charge period is after the discharge period.
摘要翻译： 提供了一种感测装置和数据感测方法。 感测装置包括初始电路，参考电流发生器和感测电路。 初始电路在放电期间将感测端放电到参考地，并且在预充电期间根据输出信号将感测端预充电到预设电压电平。 参考电流发生器从感测端吸取参考电流。 感测电路感测感测端的电压电平以产生输出信号。 其中，感测端从存储单元接收单元电流，并且预充电周期在放电周期之后。
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公开(公告)号：US20220199178A1
公开(公告)日：2022-06-23
申请号：US17469828
申请日：2021-09-08
发明人： Chieh-Tse Lee , Ting-Yang Yen , Cheng-Da Huang , Chun-Hung Lin
摘要： When a driving circuit of an anti-fuse memory device programs a selected anti-fuse memory cell, voltage differences between unselected bit lines and unselected anti-fuse control lines would be eliminated or decreased to an acceptable value by floating unselected anti-fuse control lines or by applying a second control line voltage to the unselected anti-fuse control lines. Leakage currents flowing from unselected bit lines through ruptured anti-fuse transistors of the anti-fuse memory device to the unselected anti-fuse control lines would be decreased or eliminated, and program disturbance would be avoided.
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公开(公告)号：US09792968B2
公开(公告)日：2017-10-17
申请号：US15406800
申请日：2017-01-16
发明人： Chih-Chun Chen , Chun-Hung Lin , Cheng-Da Huang
CPC分类号： G11C17/18 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/1076 , G06F12/1408 , G06F21/72 , G06F21/73 , G06F2212/1052 , G06F2212/402 , G11C5/063 , G11C7/10 , G11C7/22 , G11C7/24 , G11C16/0408 , G11C16/08 , G11C16/22 , G11C16/24 , G11C16/26 , G11C16/32 , G11C17/16 , G11C29/785 , H01L27/11206 , H03K3/356113 , H04L9/3278
摘要： A self-timed reset pulse generator includes a flip-flop, a tracking block, and a tracking circuit. The flip-flop receives an input signal and a feedback signal and outputting a reset signal. The tracking block has replicating cells coupled in series and replicates a structure in an external device. The tracking block has a first terminal and a second terminal. The first terminal and the second terminal are taking from the tracking block at a same location or two different locations. The tracking circuit unit receives the reset signal and receives the first terminal and the second terminal for respectively discharging the tracking block at the first terminal and sensing a voltage level at the second terminal as triggered by the reset signal. A track-out signal serving as the feed back signal is output to the flip-flop when the voltage level is less than or equal to a threshold.
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公开(公告)号：US20170206946A1
公开(公告)日：2017-07-20
申请号：US15406800
申请日：2017-01-16
发明人： Chih-Chun Chen , Chun-Hung Lin , Cheng-Da Huang
CPC分类号： G11C17/18 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/1076 , G06F12/1408 , G06F21/72 , G06F21/73 , G06F2212/1052 , G06F2212/402 , G11C5/063 , G11C7/10 , G11C7/22 , G11C7/24 , G11C16/0408 , G11C16/08 , G11C16/22 , G11C16/24 , G11C16/26 , G11C16/32 , G11C17/16 , G11C29/785 , H01L27/11206 , H03K3/356113 , H04L9/3278
摘要： A self-timed reset pulse generator includes a flip-flop, a tracking block, and a tracking circuit. The flip-flop receives an input signal and a feedback signal and outputting a reset signal. The tracking block has replicating cells coupled in series and replicates a structure in an external device. The tracking block has a first terminal and a second terminal. The first terminal and the second terminal are taking from the tracking block at a same location or two different locations. The tracking circuit unit receives the reset signal and receives the first terminal and the second terminal for respectively discharging the tracking block at the first terminal and sensing a voltage level at the second terminal as triggered by the reset signal. A track-out signal serving as the feed back signal is output to the flip-flop when the voltage level is less than or equal to a threshold.
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公开(公告)号：US20200159273A1
公开(公告)日：2020-05-21
申请号：US16558144
申请日：2019-09-01
发明人： Jen-Yu Peng , Chun-Hung Lin , Cheng-Da Huang
IPC分类号： G05F3/30
摘要： A reference voltage generator includes an output terminal, a current source, a reference circuit, a protection circuit, and a control circuit. The output terminal outputs a reference voltage. The current source is coupled to the output terminal, and generates a reference current. The reference circuit is coupled to the output terminal, and generates a reference voltage according to the reference current. The protection circuit is coupled to the output terminal, and adjusts a voltage of the output terminal to an operating voltage. The control circuit is coupled to the reference circuit and the protection circuit. The control circuit controls the reference circuit and the protection circuit according to a start signal.
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公开(公告)号：US10283511B2
公开(公告)日：2019-05-07
申请号：US15465616
申请日：2017-03-22
发明人： Yi-Hung Li , Ming-Shan Lo , Cheng-Da Huang
IPC分类号： H01L27/11524 , H01L23/31 , H01L23/528 , H01L29/06 , H01L29/49 , G11C7/14 , G11C16/28 , G11C16/10 , G11C16/30 , G11C16/34 , G11C29/02 , G11C5/14
摘要： A non-volatile memory including memory cells is provided. Each of the memory cells includes a substrate, a floating gate structure, a select gate structure, and a first doped region. The floating gate structure is disposed on the substrate. The select gate structure is disposed on the substrate and located at one side of the floating gate structure. The first doped region is disposed in the substrate at another side of the floating gate structure. The first doped regions between two adjacent memory cells are adjacent to one another and separated from one another.
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公开(公告)号：US10176883B2
公开(公告)日：2019-01-08
申请号：US15402242
申请日：2017-01-10
发明人： Chieh-Tse Lee , Chih-Chun Chen , Cheng-Da Huang , Chun-Hung Lin
IPC分类号： G06F3/06 , G11C5/06 , G11C17/18 , G11C17/16 , H04L9/32 , G11C29/00 , G11C16/22 , G11C7/24 , G06F21/73 , G11C16/04 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/32 , G06F11/10 , G06F21/72 , H03K3/356 , G11C7/10 , G11C7/22 , G06F12/14 , H01L27/112
摘要： A power-up sequence protection circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. First terminals of the first transistor, the second transistor, and the fourth transistor are coupled for receiving a program voltage. A control terminal of the third transistor is used for receiving a device voltage. A second terminal of the fourth transistor is used for outputting the program voltage when the fourth transistor is turned on. When the program voltage is unexpectedly powered up while the device voltage is not powered up, the first transistor is turned on, the second transistor is turned off, and the fourth transistor is turned off so as to block the program voltage outputted from the second terminal of the fourth transistor.
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