公开(公告)号：US12287753B2

公开(公告)日：2025-04-29

申请号：US18216908

申请日：2023-06-30

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gordon Caruk ,  Maurice B. Steinman ,  Gerald R. Talbot ,  Joseph D. Macri

IPC: G06F13/20 ,  G06F13/16 ,  G06F13/42

Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a non-PCIe format, encapsulating the non-PCIe format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.

公开(公告)号：US12277020B2

公开(公告)日：2025-04-15

申请号：US17561837

申请日：2021-12-24

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Joseph Lee Greathouse ,  Adam Neil Calder Clark ,  Stephen Kushnir

IPC: G06F1/3296 ,  G06F1/20 ,  G06F1/3206 ,  G06F1/3215 ,  G06F1/324

Abstract: One or more components of a computing device are run by default in a boost mode state. The one or more components continue to run in the boost mode state until the boost mode state is no longer sustainable, e.g., due to power consumption of the one or more components or temperature of the one or more components. The one or more components are switched to a reduced power state (e.g., a non-boost mode state) in response to the boost mode state no longer being sustainable. When operating the one or more components in the boost mode state again becomes sustainable due to power consumption or temperature of the one or more components, the one or more components are returned to the default boost mode state.

公开(公告)号：US20250111606A1

公开(公告)日：2025-04-03

申请号：US18375046

申请日：2023-09-29

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Paritosh Vijay Kulkarni ,  Ikeda Sho ,  Takahiro Harada

IPC: G06T17/00 ,  G06T17/20

Abstract: A fused bounding volume hierarchy, which is a combination of a base bounding volume hierarchy and one or more non-base bounding volume hierarchies, is generated. For each non-base bounding volume hierarchy, multiple subtrees in the non-base bounding volume hierarchy that include less than a threshold number of child nodes are identified. Each of these subtrees is then fused with the base bounding volume hierarchy at one of the nodes of the base bounding volume hierarchy, and an identifier of the level of detail for the non-base bounding volume hierarchy is included in the node. When displaying a scene or image, for a particular portion of the scene or image the level of detail to use is identified. The fused bounding volume hierarchy is traversed and the geometric objects in the nodes of the fused bounding volume hierarchy corresponding to the identified level of detail are displayed.

公开(公告)号：US20250111598A1

公开(公告)日：2025-04-03

申请号：US18477375

申请日：2023-09-28

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michal Adam Wozniak ,  Guennadi Riguer

IPC: G06T15/80 ,  G06T15/04

Abstract: A technique for rendering is provided. The technique includes performing a visibility operation to generate shade space visibility information and reconstruction information; performing a shade space shading operation based on the shade space visibility information generate shaded shade space textures; and performing a reconstruction operation based on the reconstruction information and the shaded shade space textures.

公开(公告)号：US20250110798A1

公开(公告)日：2025-04-03

申请号：US18792235

申请日：2024-08-01

Applicant: ATI TECHNOLOGIES ULC

Inventor： INDRANI PAUL ,  LEONARDO DE PAULA ROSA PIGA ,  MAHESH SUBRAMONY ,  SONU ARORA ,  DONALD CHEREPACHA ,  ADAM N C CLARK

IPC: G06F9/50 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/30 ,  G06F11/34

Abstract: Methods and apparatus employ a plurality of heterogeneous compute units and a plurality of non-compute units operatively coupled to the plurality of compute units. Power management logic (PML) determines a memory bandwidth level associated with a respective workload running on each of a plurality of heterogeneous compute units on the IC, and adjusts a power level of at least one non-compute unit of a memory system on the IC from a first power level to a second power level, based on the determined memory bandwidth levels. Memory access latency is also taken into account in some examples to adjust a power level of non-compute units.

公开(公告)号：US20250110525A1

公开(公告)日：2025-04-03

申请号：US18478880

申请日：2023-09-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Paul Blinzer ,  Maulik Ojas Mankad ,  Victor Ignatski ,  Ashish Jain ,  Gia Phan ,  Ranjeet Kumar

IPC: G06F1/08 ,  G06F21/64 ,  G06F21/73 ,  H01L23/525

Abstract: A computer-implemented method for enabling a feature of a semiconductor device can include receiving, by at least one processor of a semiconductor device, a command to enable a feature of the semiconductor device. The method can also include burning, by the at least one processor and in response to the command, an electronic fuse of the semiconductor device. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20250104328A1

公开(公告)日：2025-03-27

申请号：US18372991

申请日：2023-09-26

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： David William John Pankratz ,  Michael John Livesley

IPC: G06T15/06 ,  G06T15/80 ,  G06T17/00

Abstract: A processor employs work items to manage traversal of an acceleration structure, such as a ray tracing structure, at a hardware traversal engine of a processing unit. The work items are structures having a relatively small memory footprint, where each work item is associated both with a ray and with a corresponding portion of the acceleration structure. The hardware traversal engine employs a work items to manage the traversal of the corresponding portion of the acceleration structure for the corresponding ray.

公开(公告)号：US20250103090A1

公开(公告)日：2025-03-27

申请号：US18476082

申请日：2023-09-27

Applicant: ATI Technologies ULC

Inventor： Shaofeng An ,  YanFeng Wang

IPC: G06F1/08

Abstract: An exemplary method for dynamically changing frequencies of clocks for the data link layer without downtime involves switching a first queue on a first end of a data link and a second queue on a second end of the data link from a pacing mode to an asynchronous mode. The exemplary method also involves modifying a frequency of a clock associated with the data link. The exemplary method further involves returning the first queue and the second queue from the asynchronous mode to the pacing mode upon modifying the frequency of the clock. Various other devices, systems, and methods are also disclosed.

公开(公告)号：US12248423B2

公开(公告)日：2025-03-11

申请号：US18163620

申请日：2023-02-02

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Buheng Xu ,  Dong Yu ,  Philip Ng ,  Lianji Cheng

IPC: G06F13/42

Abstract: An apparatus includes logic circuitry that selects a retag transaction identifier for an original transaction identifier of an incoming transaction request, based on a plurality of sub-groups of retag tracking data. Each sub-group of retag tracking data is associated with a corresponding sub-group of retag transaction identifiers in a group of retag transaction identifiers. The logic circuitry retags the incoming transaction request with the selected retag transaction identifier (ID) by replacing the original transaction identifier associated with the incoming transaction request and sends the retagged incoming transaction request to a target. A returned response is received from the target. The retag transaction ID in the returned response is removed and replaced with the original transaction ID before being sent as a reply to the requesting unit. Associated methods are also presented.

公开(公告)号：US12190847B2

公开(公告)日：2025-01-07

申请号：US17407981

申请日：2021-08-20

Applicant: ATI Technologies ULC

Inventor： Keith Lee ,  David I. J. Glen ,  Jie Zhou ,  Yuxin Chen

IPC: G09G5/02 ,  G09G5/06

Abstract: Systems, apparatuses, and methods for reducing three dimensional (3D) lookup table (LUT) interpolation error while minimizing on-chip storage are disclosed. A processor generates a plurality of mappings from a first gamut to a second gamut at locations interspersed throughout a 3D representation of the pixel component space. For example, in one implementation, the processor calculates mappings for 17×17×17 vertices within the 3D representation. Other implementations can include other numbers of vertices. Rather than increasing the number of vertices to reduce interpolation error, the processor calculates mappings for centroids of the sub-cubes defined by the vertices within the 3D representation of the first gamut. This results in a smaller increase to the LUT size as compared to increasing the number of vertices. The centroid mappings are used for performing tetrahedral interpolation to map source pixels in the first gamut into the second gamut with a reduced amount of interpolation error.