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    Bi-directional trimming methods and circuits for a precise band-gap reference
    1.
    发明授权
    Bi-directional trimming methods and circuits for a precise band-gap reference 有权
    用于精确带隙参考的双向修整方法和电路

    公开(公告)号：US08193854B2

    公开(公告)日：2012-06-05

    申请号：US12651993

    申请日：2010-01-04

    申请人： Xiao Fei Kuang ,  Kam Chuen Wan ,  Kwai Chi Chan ,  Yat To (William) Wong ,  Kwok Kuen (David) Kwong

    发明人： Xiao Fei Kuang ,  Kam Chuen Wan ,  Kwai Chi Chan ,  Yat To (William) Wong ,  Kwok Kuen (David) Kwong

    IPC分类号： G05F3/02

    CPC分类号： G05F3/30 ,  H01C17/22

    摘要： A bandgap reference circuit has trimming-up resistors and trimming-down resistors for bi-directional trimming. PNP transistors have base and collectors grounded and emitters connected to parallel resistors. A difference resistor drives an inverting input of an op amp that drives a transistor that generates the bandgap reference voltage Vbg. A sensing resistor connects Vbg to a splitting node that connects to the non-inverting input through a first parallel resistor. The splitting node also connects through a second parallel resistor to the inverting input. Fuses or switches enable the trimming-up and trimming-down resistors. The trimming-up resistors are in series with the sensing resistor and the trimming-down resistors are in series with an output resistor that connects Vbg to reference voltage Vref. The circuit can be designed for a more typical process since bi-directional trimming allows Vref to be raised or lowered. Many circuits need no trimming when targeted for the typical process.

    摘要翻译： 带隙参考电路具有用于双向修剪的微调电阻和微调电阻。 PNP晶体管的基极和集电极接地，发射极连接到并联电阻。 差分电阻驱动驱动产生带隙参考电压Vbg的晶体管的运算放大器的反相输入。 感测电阻器将Vbg连接到通过第一并联电阻器连接到非反相输入的分离节点。 分离节点还通过第二并联电阻器连接到反相输入端。 保险丝或开关使能微调和微调电阻。 修整电阻与感测电阻串联，并且减法电阻与将Vbg连接到参考电压Vref的输出电阻串联。 该电路可以设计用于更典型的工艺，因为双向修整允许Vref被升高或降低。 许多电路在针对典型过程时不需要修剪。

    Programmable electro-magnetic-interference (EMI) reduction with enhanced noise immunity and process tolerance
    2.
    发明授权
    Programmable electro-magnetic-interference (EMI) reduction with enhanced noise immunity and process tolerance 有权
    可编程电磁干扰（EMI）降低，增强抗噪声和工艺容差

    公开(公告)号：US08188798B1

    公开(公告)日：2012-05-29

    申请号：US12948896

    申请日：2010-11-18

    申请人： Chi Tak (Gerry) Leung ,  Chik Wai (David) Ng ,  Hing Kit Kwan ,  Wai Kit (Victor) So ,  Po Wah (Patrick) Chang ,  Wing Cheong Mak ,  Kwok Kuen (David) Kwong

    发明人： Chi Tak (Gerry) Leung ,  Chik Wai (David) Ng ,  Hing Kit Kwan ,  Wai Kit (Victor) So ,  Po Wah (Patrick) Chang ,  Wing Cheong Mak ,  Kwok Kuen (David) Kwong

    IPC分类号： H03B29/00 ,  H03K3/26

    CPC分类号： H03L7/08

    摘要： A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC.

    摘要翻译： 频率抖动电路通过扩展时钟的频谱来减少引起电磁干扰（EMI）的辐射。 该时钟是将数字计数值驱动到数模转换器（DAC）的计数器。 DAC输出宽电压摆幅的锯齿波。 减法器缩小电压摆幅，产生用作上限电压的减小摆动锯齿波。 当电流泵对电容器充电和放电超过电压限制时，比较器触发设置复位锁存器来切换时钟。 由于上限电压是来自减法器的减少的锯齿波，所以对电容器充电的时间量变化，使时钟的周期抖动。 可以通过对减法器中的反馈电阻进行编程来调整抖动度。 减法器可降低抖动对DAC误差的灵敏度，从而实现廉价，精度更低的DAC。